Robin Gong [Fri, 1 Nov 2013 03:36:03 +0000 (11:36 +0800)]
ENGR00285897 mx6 busfreq: fix system crash while enter low bus with 'maxcpus=1'
Use for_each_online_cpu instead of for_each_present_cpu to take this case,
otherwise system will crash as below when go into low bus with 'maxcpus=1'
setting in command line.
Bug log during kernel boot:
...
failed to find fsl,imx6q-iomux-gpr regmap
...
The issue is imx6q_1588_init() is called before of_platform_populate().
of_platform_populate() walks the device tree and creates devices from
nodes. imx6q_1588_init() call syscon_regmap_lookup_by_compatible() to
get the device base on the given device node, since the device cannot
created for the node, so it is failed.
So, move the 1588 init function to behind of of_platform_populate().
Huang Shijie [Fri, 17 May 2013 03:17:27 +0000 (11:17 +0800)]
mtd: add data structures for Extended Parameter Page
Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
to store the ECC info.
The onfi spec tells us that if the nand chip's recommended ECC codeword
size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then
read the Extended ECC information that is part of the extended parameter
page to retrieve the ECC requirements for this device.
This patch adds
[1] the neccessary fields for nand_onfi_params{},
[2] and adds the onfi_ext_ecc_info{} for Extended ECC information,
[3] adds onfi_ext_section{} for extended sections,
[4] and adds onfi_ext_param_page{} for the Extended Parameter Page.
Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
[Brian: amended for checkpatch.pl] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Fri, 16 Aug 2013 02:10:04 +0000 (10:10 +0800)]
mtd: add a new ecc_step_size field to mtd_info{}
In order to implement the NAND boot for some Freescale's chips, such as
imx23/imx28/imx50/imx6, we use a tool (called kobs-ng) to burn the uboot
and some metadata to nand chip. And the ROM code will use the metadata to
configrate the BCH, and to find the uboot.
The ECC information(ecc step size, ecc strength) which is used to configrure
the BCH is part of the metadata. The kobs-ng can get the ecc strength from
the sys node /sys/*/ecc_strength now. But it can not get the ecc step size.
This patch adds a new field to store the ecc step size in mtd_info{}, and
it makes preparation for the next patches.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Wed, 28 Aug 2013 01:45:10 +0000 (18:45 -0700)]
mtd: nand: hack ONFI for non-power-of-2 dimensions
Some bright specification writers decided to write this in the ONFI spec
(from ONFI 3.0, Section 3.1):
"The number of blocks and number of pages per block is not required to
be a power of two. In the case where one of these values is not a
power of two, the corresponding address shall be rounded to an
integral number of bits such that it addresses a range up to the
subsequent power of two value. The host shall not access upper
addresses in a range that is shown as not supported."
This breaks every assumption MTD makes about NAND block/chip-size
dimensions -- they *must* be a power of two!
And of course, an enterprising manufacturer has made use of this lovely
freedom. Exhibit A: Micron MT29F32G08CBADAWP
"- Plane size: 2 planes x 1064 blocks per plane
- Device size: 32Gb: 2128 blockss [sic]"
This quickly hits a BUG() in nand_base.c, since the extra dimensions
overflow so we think it's a second chip (on my single-chip setup):
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0x44 (Micron MT29F32G08CBADAWP), 4256MiB, page size: 8192, OOB size: 744
------------[ cut here ]------------
kernel BUG at drivers/mtd/nand/nand_base.c:203!
Internal error: Oops - BUG: 0 [#1] SMP ARM
[... trim ...]
[<c02cf3e4>] (nand_select_chip+0x18/0x2c) from [<c02d25c0>] (nand_do_read_ops+0x90/0x424)
[<c02d25c0>] (nand_do_read_ops+0x90/0x424) from [<c02d2dd8>] (nand_read+0x54/0x78)
[<c02d2dd8>] (nand_read+0x54/0x78) from [<c02ad2c8>] (mtd_read+0x84/0xbc)
[<c02ad2c8>] (mtd_read+0x84/0xbc) from [<c02d4b28>] (scan_read.clone.4+0x4c/0x64)
[<c02d4b28>] (scan_read.clone.4+0x4c/0x64) from [<c02d4c88>] (search_bbt+0x148/0x290)
[<c02d4c88>] (search_bbt+0x148/0x290) from [<c02d4ea4>] (nand_scan_bbt+0xd4/0x5c0)
[... trim ...]
---[ end trace 0c9363860d865ff2 ]---
So to fix this, just truncate these dimensions down to the greatest
power-of-2 dimension that is less than or equal to the specified
dimension.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Current code sets the mtd->type with MTD_NANDFLASH for both
SLC and MLC. So the jffs2 may supports the MLC nand, but in actually,
the jffs2 should not support the MLC.
This patch uses the nand_is_slc() to check the nand cell type,
and set the mtd->type with the right nand type.
After this patch, the jffs2 only supports the SLC nand.
The side-effect of this patch:
Before this patch, the ioctl(MEMGETINFO) can only return with the
MTD_NANDFLASH; but after this patch, the ioctl(MEMGETINFO) will
return with the MTD_NANDFLASH for SLC, and MTD_MLCNANDFLASH for MLC.
So the user applictions(such as mtd-utils) should also changes a little
for this.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Huang Shijie [Fri, 17 May 2013 03:17:31 +0000 (11:17 +0800)]
mtd: add ECC info for nand_flash_dev{}
Add an instance of an anonymous struct to store the ECC info for full id
nand chips.
@ecc.strength_ds: ECC correctability from the datasheet.
@ecc.step_ds: ECC size required by the @ecc.strength_ds,
These two fields are all from the datasheet.
Also add the necessary macros to make the code simple and clean.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Fri, 17 May 2013 03:17:25 +0000 (11:17 +0800)]
mtd: add datasheet's ECC information to nand_chip{}
1.) Why add the ECC information to the nand_chip{} ?
Each nand chip has its requirement for the ECC correctability, such as
"4bit ECC for each 512Byte" or "40bit ECC for each 1024Byte".
This ECC info is very important to the nand controller, such as gpmi.
Take the Micron MT29F64G08CBABA for example, its geometry is
8KiB page size, 744 bytes oob size and it requires 40bit ECC per 1KiB.
If we do not provide the ECC info to the gpmi nand driver, it has to
calculate the ECC correctability itself. The gpmi driver will gets the 56bit
ECC for per 1KiB which is beyond its BCH's 40bit ecc capibility.
The gpmi will quits in this case. But in actually, the gpmi can supports
this nand chip if it can get the right ECC info.
2.) about the new fields.
The @ecc_strength_ds stands for the ecc bits needed within the @ecc_step_ds.
The two fields should be set from the nand chip's datasheets.
For example:
"4bit ECC for each 512Byte" could be:
@ecc_strength_ds = 4, @ecc_step_ds = 512.
"40bit ECC for each 1024Byte" could be:
@ecc_strength_ds = 40, @ecc_step_ds = 1024.
3.) Why do not re-use the @strength and @size in the nand_ecc_ctrl{}?
The @strength and @size in nand_ecc_ctrl{} is used by the nand controller
driver, while the @ecc_strength_ds and @ecc_step_ds are get from the datasheet.
Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Thu, 11 Apr 2013 08:34:59 +0000 (01:34 -0700)]
mtd: nand: reword nand_chip bad block interface comments
This remedies a few problems:
(1) The use of "the" vs. "a" is a little confusing, IMO.
(2) nand_chip.block_bad is used exclusively for checking the OOB bad
block markers of a NAND. Any BBT functionality is handled in
nand_bbt.c, so this description should differentiate itself from
nand_bbt.c.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
If the ONFI extended parameter page gives codeword_size == 0, the
extended ECC information is corrupt and should not be used. Currently,
we (correctly) avoid using the information, but we don't report the
error to the caller, so the caller doesn't know that we didn't
initialize ecc_strength_ds and ecc_step_ds. Now the caller can warn the
user that it does not have sufficient information.
This also removes the false and useless "ONFI extended param page
detected" debug message (it was printed even on the aforementioned
corruption, and for the success case, we don't really want a print).
Brian Norris [Tue, 13 Aug 2013 17:51:55 +0000 (10:51 -0700)]
mtd: nand: cleanup ONFI printed errors, warnings
The ONFI detection routine is too verbose in some cases and not verbose
enough in others. This patch refactors it to print only when there are
significant warnings/errors.
Probing in 16-bit mode:
It is unnecessary to print until after the READID (address 20h)
command. READID *has* to work properly in whatever bus width
configuration we are in, or else no identification mode works. So we
can silence some useless warnings on systems which come up in 16-bit
mode and do not even respond with an O-N-F-I string.
Valid parameter page:
Nobody needs to see this. Do we inform the user every time other
hardware responds properly? Instead, add an error message if *no*
uncorrupted parameter pages are found.
ONFI ECC:
Most drivers don't yet use the reported minimum ECC values, so it
shouldn't yet be a fatal condition if the extended parameter page is
incorrect. But we should at least give a warning for the corner cases
that we don't expect.
ONFI flash detected:
Nobody needs to see this. This is the expected case, that we detect
ONFI properly, or else it wasn't ONFI-compliant and is detected by
some other routine.
Dan Carpenter [Fri, 9 Aug 2013 09:49:05 +0000 (12:49 +0300)]
mtd: nand: silence some shift wrap warnings
There are static checkers which complain when we declare variables as
64 bit bitfields but only use the lower 32 bits because of shift
wrapping. In this case "len" is declared as u64 as opposed to unsigned
long or something which might be 32 bits.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Huang Shijie [Fri, 17 May 2013 03:17:30 +0000 (11:17 +0800)]
mtd: replace the hardcode with the onfi_feature()
The current code uses the hardcode to detect the 16-bit bus width.
Use the onfi_feature() to replace it.
Signed-off-by: Huang Shijie <b32955@freescale.com>
[Brian: small fixup] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Wed, 22 May 2013 02:28:27 +0000 (10:28 +0800)]
mtd: get the ECC info from the Extended Parameter Page
Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
to store the ECC info.
The onfi spec tells us that if the nand chip's recommended ECC codeword
size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then
read the Extended ECC information that is part of the extended parameter
page to retrieve the ECC requirements for this device.
This patch implement the reading of the Extended Parameter Page, and parses
the sections for ECC type, and get the ECC info from the ECC section.
Tested this patch with Micron MT29F64G08CBABAWP.
Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Tue, 25 Jun 2013 20:17:59 +0000 (13:17 -0700)]
mtd: nand: detect OOB size for Toshiba 24nm raw SLC
Toshiba NAND datasheets have not been very forthcoming on OOB size
information; they do not provide any bitfields in the ID string for
spare area. In their 24nm technology flash, however, Toshiba migrated
their NAND to have 32 bytes spare per 512 bytes of page area (up from
the traditional 16 bytes), as they now require 8-bit ECC or higher.
I have discussed this issue directly with Toshiba representatives, and
they acknowledge this problem. They recommend detecting these flash
based on their technology node as follows:
For 24nm Toshiba SLC raw NAND (not BENAND -- Built-in Ecc NAND), there
are 32 bytes of spare area for every 512 bytes of in-band data area.
We can implement this rule with the following snippet of a device ID
decode table, which applies to all their 43nm, 32nm, and 24nm SLC NAND
(this table is not fully in the NAND datasheets, but it was provided
directly by Toshiba representatives):
Brian Norris [Sat, 10 Aug 2013 08:09:49 +0000 (01:09 -0700)]
mtd: nand: stop exporting nand_default_bbt
I removed the last non-nand_base users of this, and we shouldn't have
any more modules that need to access it. It's only non-static to share
between nand_base and nand_bbt.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Brian Norris [Wed, 31 Jul 2013 00:53:00 +0000 (17:53 -0700)]
mtd: nand: remove NAND_BBT_SCANEMPTY
NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its
single remaining user.
NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway,
omap2 doesn't scan the chip for bad blocks (courtesy of
NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant.
nand_base.c shouldn't have to know the implementation details of
nand_bbt's in-memory BBT. Specifically, nand_base shouldn't perform the
bit masking and shifting to isolate a BBT entry.
Instead, just move some of the BBT code into a new nand_markbad_bbt()
interface. This interface allows external users (i.e., nand_base) to
mark a single block as bad in the BBT. Then nand_bbt will take care of
modifying the in-memory BBT and updating the flash-based BBT (if
applicable).
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
/*
* Note that numblocks is 2 * (real numblocks) here, see i+=2
* below as it makes shifting and masking less painful
*/
I don't think it ever could have been "less painful" to have to shift an
extra bit (or 2, or 3) at various points in nand_bbt.c (and even
outside, since we leak our in-memory format). But now it is certainly
more painful, since we have nice macros and functions to retrieve the
relevant portions of the BBT.
This patch removes any points where the block number is
doubled/halved/otherwise-shifted, instead representing the block number
in its most natural form: as the actual block number.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Brian Norris [Wed, 31 Jul 2013 00:52:55 +0000 (17:52 -0700)]
mtd: nand: add accessors, macros for in-memory BBT
There is an abundance of magic numbers and complicated shifting/masking
logic in the in-memory BBT code which makes the code unnecessary complex
and hard to read.
This patch adds macros to represent the 00b, 01b, 10b, and 11b
memory-BBT magic numbers, as well as two accessor functions for reading
and marking the memory-BBT bitfield for a given block.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Huang Shijie [Tue, 27 Aug 2013 09:29:07 +0000 (17:29 +0800)]
mtd: gpmi: imx6: fix the wrong method for checking ready/busy
In the imx6, all the ready/busy pins are binding togeter.
So we should always check the ready/busy pin of the chip 0.
In the other word, when the CS1 is enabled, we should also check the
ready/busy of chip 0; if we check the ready/busy of chip 1,
we will get the wrong result.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
David Woodhouse [Fri, 25 Oct 2013 14:03:59 +0000 (15:03 +0100)]
mtd: gpmi: fix ECC regression
The "legacy" ECC layout used until 3.12-rc1 uses all the OOB area by
computing the ECC strength and ECC step size ourselves.
Commit 2febcdf84b ("mtd: gpmi: set the BCHs geometry with the ecc info")
makes the driver use the ECC info (ECC strength and ECC step size)
provided by the MTD code, and creates a different NAND ECC layout
for the BCH, and use the new ECC layout. This causes a regression:
We can not mount the ubifs which was created by the old NAND ECC layout.
This patch fixes this issue by reverting to the legacy ECC layout.
We will probably introduce a new device-tree property to indicate that
the new ECC layout can be used. For now though, for the imminent 3.12
release, we just unconditionally revert to the 3.11 behaviour.
This leaves a harmless cosmetic warning about an unused function. At
this point in the cycle I really don't care.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
Huang Shijie [Fri, 16 Aug 2013 02:10:08 +0000 (10:10 +0800)]
mtd: gpmi: remove the nand_scan()
In order to make the nand_scan() work, the current code uses the hack code
to init the @nand_chip->ecc.size and the @nand_chip->ecc.strength. and
re-init some the ECC info in the gpmi_pre_bbt_scan().
This code is really a little ugly.
The patch does following changes:
(1) Use the nand_scan_ident()/nand_scan_tail() to replace the nand_scan().
(2) Init all the necessary values in the gpmi_init_last()
before we call the nand_scan_tail().
(3) remove the code setting the ECC info, let the mtd layer to do the
real job.
(4) remove the gpmi_scan_bbt(). we do not need this function any more.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Fri, 17 May 2013 03:17:34 +0000 (11:17 +0800)]
mtd: gpmi: set the BCH's geometry with the ecc info
If the nand chip provides us the ECC info, we can use it firstly.
The set_geometry_by_ecc_info() will use the ECC info, and
calculate the parameters we need.
Rename the old code to legacy_set_geometry() which will takes effect
when there is no ECC info from the nand chip or we fails in the ECC info case.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Wed, 31 Jul 2013 00:52:58 +0000 (17:52 -0700)]
mtd: nand: refactor chip->block_markbad interface
The chip->block_markbad pointer should really only be responsible for
writing a bad block marker for new bad blocks. It should not take care
of BBT-related functionality, nor should it handle bookkeeping of bad
block stats.
This patch refactors the 3 users of the block_markbad interface (plus
the default nand_base implementation) so that the common code is kept in
nand_block_markbad_lowlevel(). It removes some inconsistencies between
the various implementations and should allow for more centralized
improvements in the future.
Because gpmi-nand no longer needs the nand_update_bbt() function, let's
stop exporting it as well.
Wolfram Sang [Wed, 10 Jul 2013 15:57:41 +0000 (16:57 +0100)]
mtd: gpmi-nand: don't use devm_pinctrl_get_select_default() in probe
Since commit ab78029 (drivers/pinctrl: grab default handles from device core),
we can rely on device core for setting the default pins. Compile tested only.
Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d0631001288a5974afc0b2a5f568bcdecb4d
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Luwei Zhou [Wed, 30 Oct 2013 06:24:34 +0000 (14:24 +0800)]
ENGR00285441 mxc: mlb: Fix the receive issue of ISOC mode on Sabreauto
This patch fixes the receive issue of MLB ISO mode on Sabreauto side.
During debug, it is found that the Sabreauto can only receive
1/5 packets of MITB sends.The MITB sends out 188 bytes per packet.
The Sabreauto receives 188*5 bytes. It seems that the packet length
on Sabreauto side is 5 times larger than MITB side. After changing
the defautl block number to 1, Sabreauto passes the test.
- Configure boot partition
Expose the interfaces that used to enable the configurations
of the boot mode of the eMMC cards.
usage how-to and examples:
Enable the boot partition 1 boot enabled.
"echo 8 > /sys/devices/soc0/soc.1/2100000.aips-bus/ 219c000.usdhc/mmc_host/mmc2/mmc2\:0001/boot_config"
In order to make sure that the re-read the ext-csd of card
can be completed successfully, add the method to wait for
the finish of the busy state.
- setup boot_info message output
Output bit means of important esd_csd register
Read esd_csd info each time when cat boot_info
becasue user may change config affect esd_csd
value.
- Boot partition access howto:
About the details, please refer to the guidance of
Documentation/mmc/mmc-dev-parts.txt
To enable write access to /dev/mmcblkXbootY, disable the forced
read-only access with:
echo 0 > /sys/block/mmcblkXbootY/force_ro
To re-enable read-only access:
echo 1 > /sys/block/mmcblkXbootY/force_ro
NOTE:
- The definitions of the EXT_CSD_PART_CONFIG and EXT_CSD_BOOT_BUS_WIDTH
+------------------------------------------------------------+
| Bit7 | Bit6 | Bit5 Bit4 Bit3 | Bit2 Bit1 Bit0 |
|------|----------|-----------------------|------------------|
| X | BOOT_ACK | BOOT_PARTITION_ENABLE | PARTITION_ACCESS |
+------------------------------------------------------------+
Bit7: Reserved
Bit6: always set to vaule '1' when boot_part is enabled
Bit[5:3]:
0x0 : Device not boot enabled (default)
0x1 : Boot partition 1 enabled for boot
0x2 : Boot partition 2 enabled for boot
0x7 : User area enabled for boot
Bit[2:0]:
0x0 : No access to boot partition (default)
0x1 : R/W boot partition 1
0x2 : R/W boot partition 2
+--------------------------------------------------------------------+
| Bit7 Bit6 Bit5 | Bit4 Bit3 | Bit2 | Bit1 Bit0 |
|----------------|----------------------------------|----------------|
| X | BOOT_MODE | RESET_BOOT_BUS_WIDTH | BOOT_BUS_WIDTH |
+--------------------------------------------------------------------+
Bit [4:3] : BOOT_MODE (non-volatile)
0x0 : Use single data rate + backward compatible timings in boot
operation (default)
0x1 : Use single data rate + high speed timings in boot operation mode
0x2 : Use dual data rate in boot operation
0x3 : Reserved
Bit [2]: RESET_BOOT_BUS_WIDTH (non-volatile)
0x0 : Reset bus width to x1, single data rate and backward compatible
timings after boot operation (default)
0x1 : Retain boot bus width and boot mode after boot operation
Bit[1:0] : BOOT_BUS_WIDTH (non-volatile)
0x0 : x1 (sdr) or x4 (ddr) bus width in boot operation mode (default)
0x1 : x4 (sdr/ddr) bus width in boot operation mode
0x2 : x8 (sdr/ddr) bus width in boot operation mode
0x3 : Reserved
- example of the boot_info:
boot_info:0x07;
ALT_BOOT_MODE:1 - Supports alternate boot method
DDR_BOOT_MODE:1 - Supports alternate dual data rate during boot
HS_BOOTMODE:1 - Supports high speed timing during boot
boot_size:2048KB
boot_partition:0x48;
BOOT_ACK:1 - Boot acknowledge sent during boot operation
BOOT_PARTITION-ENABLE: 1 - Boot partition 1 enabled
PARTITION_ACCESS:0 - No access to boot partition
boot_bus:0x00
BOOT_MODE:0 - Use single data rate + backward compatible timings
in boot operation
RESET_BOOT_BUS_WIDTH:0 - Reset bus width to x1, single data rate
and backwardcompatible timings after boot operation
BOOT_BUS_WIDTH:0 - x1 (sdr) or x4 (ddr) bus width in boot
operation mode
Xianzhong [Tue, 13 Aug 2013 15:16:24 +0000 (23:16 +0800)]
ENGR00274782 fixed gpu crash when baseAddress is not 0 or 2G
The baseAddress of contiguousVidMem is the actual physical address
which is not subtracted by gpu baseAddress, but the allocated physical address
has been subtracted by gpu baseAddress in gckVIDMEM_Lock,
so the invalid offset is produced and used to calculate the logical address.
Luwei Zhou [Tue, 22 Oct 2013 08:20:31 +0000 (16:20 +0800)]
ENGR00284648 mxc: mlb: clean up the MLB driver code.
This patch clean up the MLB driver code of i.MX6Q/DL AUTO.
* Reorder the head file alphabetically
* Fix code comments format
* Fix the lines over 80 characters
* Fix the return type to void for some private functions
Nicolin Chen [Thu, 17 Oct 2013 10:24:29 +0000 (18:24 +0800)]
ENGR00283079-1 ASoC: fsl: Implement different DMA buffer sizes
Each CPU DAI driver has its own defined DMA buffer size, so this patch just
drops the original one that uses a fixed size for all drivers and implements
a different DMA buffer size to each driver.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
Nicolin Chen [Wed, 23 Oct 2013 03:47:43 +0000 (11:47 +0800)]
ALSA: Add SoC on-chip internal ram support for DMA buffer allocation
Now it's quite common that an SoC contains its on-chip internal RAM.
By using this RAM space for DMA buffer during audio playback/record,
we can shutdown the voltage for external RAM to save power.
So add new DEV type with iram malloc()/free() and accordingly modify
current default mmap() for the iram circumstance.
attribute groups are much more flexible than just a list of attributes,
due to their support for visibility of the attributes, and binary
attributes. Add dev_groups to struct bus_type which should be used
instead of dev_attrs.
dev_attrs will be removed from the structure soon.
To make it easier for driver subsystems to work with attribute groups,
create the ATTRIBUTE_GROUPS macro to remove some of the repetitive
typing for the most common use for attribute groups.
Huang Shijie [Wed, 23 Oct 2013 08:05:42 +0000 (16:05 +0800)]
spi: spi-imx: only enable the clocks when we start to transfer a message
Current code keeps the clocks enabled all the time, it wastes the power
when there is no operaiton on the spi controller.
In order to save the power, this patch adds the two hooks:
spi_imx_prepare_message: enable the clocks for this message
spi_imx_unprepare_message: disable the clocks.
This patch also disables the clocks in the end of the probe.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Jingoo Han [Mon, 14 Oct 2013 01:31:51 +0000 (10:31 +0900)]
spi: Fix checkpatch issue
Fix the following checkpatch error and warnings.
ERROR: space required after that ',' (ctx:VxV)
WARNING: quoted string split across lines
WARNING: max() should probably be max_t(int, nb, master->num_chipselect)
WARNING: sizeof *spi should be sizeof(*spi)
WARNING: sizeof *master should be sizeof(*master)
WARNING: sizeof x should be sizeof(x)
Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Sat, 5 Oct 2013 10:50:40 +0000 (11:50 +0100)]
spi: Provide common spi_message processing loop
The loops which SPI controller drivers use to process the list of transfers
in a spi_message are typically very similar and have some error prone areas
such as the handling of /CS. Help simplify drivers by factoring this code
out into the core - if drivers provide a transfer_one() function instead
of a transfer_one_message() function the core will handle processing at the
message level.
/CS can be controlled by either setting cs_gpio or providing a set_cs
function. If this is not possible for hardware reasons then both can be
omitted and the driver should continue to implement manual /CS handling.
This is a first step in refactoring and it is expected that there will be
further enhancements, for example factoring out of the mapping of transfers
for DMA and the initiation and completion of interrupt driven transfers.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Fri, 4 Oct 2013 23:23:12 +0000 (00:23 +0100)]
spi: Provide per-message prepare and unprepare operations
Many SPI drivers perform setup and tear down on every message, usually
doing things like DMA mapping the message. Provide hooks for them to use
to provide such operations.
This is of limited value for drivers that implement transfer_one_message()
but will be of much greater utility with future factoring out of standard
implementations of that function.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mika Westerberg [Thu, 10 Oct 2013 10:28:48 +0000 (13:28 +0300)]
spi: attach/detach SPI device to the ACPI power domain
If the SPI device is enumerated from ACPI namespace (it has an ACPI handle)
it might have ACPI methods that needs to be called in order to transition
the device to different power states (such as _PSx).
We follow what has been done for platform and I2C buses here and attach the
SPI device to the ACPI power domain if the device has an ACPI handle. This
makes sure that the device is powered on when its ->probe() is called.
For non-ACPI devices this patch is a no-op.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mark Brown <broonie@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Jarkko Nikula [Thu, 10 Oct 2013 14:19:17 +0000 (17:19 +0300)]
spi: Fix modalias for ACPI enumerated SPI devices
There is a minor fault about ACPI enumerated SPI devices with their modalias
attribute. Now modalias is set by device instance not by hardware ID.
For example "spi:INTABCD:00", "spi:INTABCD:01" etc.
This means each device instance gets different modalias which does match
with generated modules.alias. Currently this is not problem as matching can
happen also with "acpi:INTABCD" modalias.
Fix this by using ACPI hardware ID.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Mon, 7 Oct 2013 18:33:53 +0000 (19:33 +0100)]
spi: Provide trace points for message processing
Provide tracepoints for the lifecycle of a message from submission to
completion and for the active time for masters to help with performance
analysis of SPI I/O.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Instead of getting the raw property, checking the length, and doing
endian conversion each time, use the OF function
of_property_read_u32() that does all that.
Error messages are slightly improved with error codes from
of_property_read_u32() for different ways the property may be invalid
(missing, too short, etc.)
Signed-off-by: Trent Piepho <tpiepho@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Sat, 31 Aug 2013 17:50:52 +0000 (18:50 +0100)]
spi: core: Add devm_spi_register_master()
Help simplify the cleanup code for SPI master drivers by providing a
managed master registration function, ensuring that the master is
automatically unregistered whenever the device is unbound.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
The previous property name spi-tx-nbits and spi-rx-nbits looks not
human-readable. To make it consistent with other devices, using property
name spi-tx-bus-width and spi-rx-bus-width instead of the previous one
specify the number of data wires that spi controller will work in.
Add the specification in spi-bus.txt.
Signed-off-by: wangyuhang <wangyuhang2014@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Axel Lin [Sat, 31 Aug 2013 12:25:52 +0000 (20:25 +0800)]
spi: core: Fix spi_register_master error handling
In the case spi_master_initialize_queue() fails, current code calls
device_unregister() before return error from spi_register_master().
However, all the drivers call spi_master_put() in the error path if
spi_register_master() fails. Thus we should call device_del() rather than
device_unregister() before return error from spi_register_master().
This also makes all the spi_register_master() error handling consistent,
because all other error paths of spi_register_master() expect drivers to
call spi_master_put() if spi_register_master() fails.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Fri, 30 Aug 2013 22:19:40 +0000 (23:19 +0100)]
spi: quad: Make DT properties optional
The addition SPI quad support made the DT properties mandatory, breaking
compatibility with existing systems. Fix that by making them optional,
also improving the error messages while we're at it.
Signed-off-by: Mark Brown <broonie@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Axel Lin [Thu, 22 Aug 2013 15:41:34 +0000 (23:41 +0800)]
spi: Remove a redundant test for master->running in spi_queued_transfer
We have tested master->running immediately after grab the master->queue_lock.
The status of master->running won't be changed until we release the lock.
Thus remove a redundant test for master->running.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Sourav Poddar [Thu, 22 Aug 2013 15:50:48 +0000 (21:20 +0530)]
spi: conditional checking of mode and transfer bits.
There is a bug in the following patch:
http://comments.gmane.org/gmane.linux.kernel.spi.devel/14420
spi: DUAL and QUAD support
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = <1/2/4>" in place of using
"spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
(1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
single, dual and quad.
(2)keep tx_nbits and rx_nbits are contained by @spi_device->mode
example: if @spi_device->mode = DUAL, then tx/rx_nbits can not be set
to QUAD(SPI_NBITS_QUAD)
(3)if "@spi_device->mode & SPI_3WIRE", then tx/rx_nbits should be in
single(SPI_NBITS_SINGLE)
Checking of the tx/rx transfer bits and mode bits should be done conditionally
based on type of buffer filled else EINVAL condition will
always get hit either for rx or tx.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
wangyuhang [Sun, 11 Aug 2013 10:15:17 +0000 (18:15 +0800)]
spi: DUAL and QUAD support
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = <1/2/4>" in place of using
"spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
(1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
single, dual and quad.
(2)keep tx_nbits and rx_nbits are contained by @spi_device->mode
example: if @spi_device->mode = DUAL, then tx/rx_nbits can not be set
to QUAD(SPI_NBITS_QUAD)
(3)if "@spi_device->mode & SPI_3WIRE", then tx/rx_nbits should be in
single(SPI_NBITS_SINGLE)
Signed-off-by: wangyuhang <wangyuhang2014@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Gabor Juhos [Wed, 14 Aug 2013 08:25:28 +0000 (10:25 +0200)]
spi: limit default transfer speed to controller's max speed
Since the 'spi: Support transfer speed checking in the core'
change, the SPI core validates the desired speed of a given
transfer against the minimum and maximum speeds supported by
the controller.
If the speed of a transfer is not specified, the core uses
the maximum speed of the actual SPI device. However if the
maximum speed of the actual device is greater than the
maximum speed of the controller, the core will reject the
transfer due to the aforementioned change.
Change the code to use the maximum speed of the controller
by default if that is below the device's maximum speed.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Stephen Warren [Thu, 1 Aug 2013 22:08:57 +0000 (16:08 -0600)]
spi: fix SPI_BIT_MASK so it always fits into 32-bits
On a 64-bit platform, ~0UL fills 64-bits, which causes SPI_BIT_MASK(32)
not to fit into 32 bits. This causes a warning when the result is assigned
to a 32-bit variable. Use ~0U instead to prevent this. This fixes:
drivers/spi/spi-gpio.c: In function 'spi_gpio_probe':
drivers/spi/spi-gpio.c:446:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]
Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Sun, 28 Jul 2013 13:47:02 +0000 (14:47 +0100)]
spi: Provide core support for runtime PM during transfers
Most SPI drivers that implement runtime PM support use identical code to
do so: they acquire a runtime PM lock in prepare_transfer_hardware() and
then they release it in unprepare_transfer_hardware(). The variations in
this are mostly missing error checking and the choice to use autosuspend.
Since these runtime PM calls are normally the only thing in the prepare
and unprepare callbacks and the autosuspend API transparently does the
right thing on devices with autosuspend disabled factor all of this out
into the core with a flag to enable the behaviour.
Signed-off-by: Mark Brown <broonie@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Stephen Warren [Thu, 30 May 2013 15:59:40 +0000 (09:59 -0600)]
spi: fix incorrect handling of min param in SPI_BPW_RANGE_MASK
SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one
representing support for all bits up-to-and-including the "max" supported
value, and one representing support for all bits up-to-but-not-including
the "min" supported value, and then taking the difference between the
two, resulting in a mask representing support for all bits between
(inclusive) the min and max values.
However, the second mask ended up representing all bits up-to-and-
including rather up-to-but-not-including. Fix this bug.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
projects / karo-tx-linux.git / log