Hauke Mehrtens [Thu, 2 Jan 2014 18:01:08 +0000 (19:01 +0100)]
bcma: prevent irq handler from firing when registered
With this patch we prevent the irq from being fired when it is
registered. The Hardware fires an IRQ when input signal XOR polarity
AND gpio mask is 1. Now we are setting polarity to a vlaue so that is
is 0 when we register it.
In addition we also set the irq mask register to 0 when the irq handler
is initialized, so all gpio irqs are masked and there will be no
unexpected irq.
BUG() can be a noop if CONFIG_BUG is not selected,
leading to the following build problem on a randconfig:
arch/mips/bcm63xx/cpu.c: In function 'detect_cpu_clock':
arch/mips/bcm63xx/cpu.c:254:1: error: control reaches end of
non-void function [-Werror=return-type]
We fix this problem by replacing BUG() with panic() since it's
best to handle the case of an unknown board instead of silently
returning a random clock frequency.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by: Jonas Gorski <jogo@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5932/
Rafał Miłecki [Thu, 2 Jan 2014 12:53:15 +0000 (13:53 +0100)]
MIPS: BCM47XX: Drop WGT634U hacks
This old wgt634u.c was trying to implement a bit ugly support for
Netgear WGT634U. It provided info about LED, flash mapping & layout and
was trying to handle reset button.
This is not needed anymore as we have replacement for all this stuff.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6302/
Rafał Miłecki [Tue, 14 Jan 2014 11:36:29 +0000 (12:36 +0100)]
MIPS: BCM47XX: Prepare support for GPIO buttons
So far this adds support for one Netgear model only, but it's designed
and ready to add many more device. We could hopefully import database
from OpenWrt.
Support for SSB is currently disabled, because SSB doesn't implement IRQ
domain yet.
Rafał Miłecki [Tue, 14 Jan 2014 11:14:41 +0000 (12:14 +0100)]
MIPS: BCM47XX: Prepare support for LEDs
So far this is mostly just a proof of concept, database consists of a
single device. Creating a nice iterateable array wasn't an option
because devices have different amount of LEDs. And we don't want to
waste memory just because of support for a device with dozens on LEDs.
Hauke Mehrtens [Sun, 22 Dec 2013 13:36:30 +0000 (14:36 +0100)]
MIPS: BCM47XX: do not use cpu_wait instruction on BCM4706
The BCM4706 has a problem with the CPU wait instruction. When r4k_wait
or r4k_wait_irqoff is used will just hang and not return from a
msleep(). Removing the cpu_wait functionality is a workaround for this
problem. The BCM4716 does not have this problem.
The BCM4706 SoC uses a MIPS 74K V4.9 CPU.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6288/
Jayachandran C [Tue, 14 Jan 2014 11:39:15 +0000 (12:39 +0100)]
MIPS: Netlogic: Core wakeup improvements
Move wakeup to after early console. This will allow us to display error
messages when cores are not woken up. Also reduce the wait time for core
to come up.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6303/
Jayachandran C [Fri, 25 Oct 2013 11:24:15 +0000 (16:54 +0530)]
MIPS: Netlogic: Remove XLR early serial setup
The early serial code is not needed because we already have early
printk support provided by common/earlycons.c
This change also fixes the following build error that occurs when
CONFIG_SERIAL_8250 is not configured for Netlogic XLR boards:
arch/mips/built-in.o: In function `nlm_early_serial_setup':
setup.c:(.init.text+0x274): undefined reference to `early_serial_setup'
make: *** [vmlinux] Error 1
Reported-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6083/
Jayachandran C [Sat, 21 Dec 2013 11:22:30 +0000 (16:52 +0530)]
MIPS: Netlogic: Add default DTB for XLP9XX SoC
Add a default device tree fie for XLP9XX boards, and add code to use
this device tree if no DTB is passed to the kernel.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6287/
Jayachandran C [Sat, 21 Dec 2013 11:22:29 +0000 (16:52 +0530)]
MIPS: Netlogic: XLP9XX PIC OF support
Support for adding legacy IRQ domain for XLP9XX. The node id of the
PIC has to be calulated differently for XLP9XX.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6286/
XLP9XX has a USB 3.0 controller on-chip with 2 xHCI ports. The USB
block is similar to the one on XLP2XX, so update usb-init-xlp2.c
to handle XLP9XX as well.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6285/
Jayachandran C [Sat, 21 Dec 2013 11:22:27 +0000 (16:52 +0530)]
MIPS: PCI: Netlogic XLP9XX support
Add PCI support for Netlogic XLP9XX. The PCI registers and
SoC bus numbers have changed in XLP9XX.
Also skip a few (bus,dev,fn) combinations which have issues when
read.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6284/
Jayachandran C [Sat, 21 Dec 2013 11:22:26 +0000 (16:52 +0530)]
MIPS: Netlogic: Add cpu to node mapping for XLP9XX
XLP9XX has 20 cores per node, opposed to 8 on earlier XLP8XX.
Update code that calculates node id from cpu id to handle this.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6283/
Jayachandran C [Sat, 21 Dec 2013 11:22:25 +0000 (16:52 +0530)]
MIPS: Netlogic: XLP9XX bridge and DRAM code
Update bridge code. Add code to the XLP9XX registers for DRAM
size, limit and node when running on XLPXX
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6282/
Jayachandran C [Sat, 21 Dec 2013 11:22:24 +0000 (16:52 +0530)]
MIPS: Netlogic: XLP9XX UART offset
Update IO offset of the early console UART.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6281/
Jayachandran C [Sat, 21 Dec 2013 11:22:23 +0000 (16:52 +0530)]
MIPS: Netlogic: SYS block updates of XLP9XX
Add the SYS block registers for XLP9XX, most of them have changed.
The wakeup sequence has been updated to set the coherent mode from
the main thread rather than the woken up thread.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6280/
Jayachandran C [Sat, 21 Dec 2013 11:22:22 +0000 (16:52 +0530)]
MIPS: Netlogic: XLP9XX PIC updates
Functions for the XLP9XX interrupt table entry format and other PIC
register changes.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6279/
Jayachandran C [Sat, 21 Dec 2013 11:22:21 +0000 (16:52 +0530)]
MIPS: Netlogic: update iomap.h for XLP9XX
Most IO block offsets have changed in XLP9XX. Update iomap.h to add the
new addresses of different SoC blocks like PIC, SYS, UART etc. that are
needed by the base code.
On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus
corresponding to the node. Update iomap code to reflect this.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6277/
Jayachandran C [Sat, 21 Dec 2013 11:22:20 +0000 (16:52 +0530)]
MIPS: Netlogic: Identify XLP 9XX chip
Adds processor ID of XLP 9XX to asm/cpu.h. Update netlogic/xlp-hal/xlp.h
to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6274/
Jayachandran C [Sat, 21 Dec 2013 11:22:18 +0000 (16:52 +0530)]
MIPS: Netlogic: Get coremask from FUSE register
Use the FUSE register to get the list of active cores in the CPU
instead of using the CPU reset register, this is the recommended
method.
Also add code to mask the coremask with the default number of cores
for each processor series.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6275/
Jayachandran C [Sat, 21 Dec 2013 11:22:17 +0000 (16:52 +0530)]
MIPS: Netlogic: Add macro for node present
Add macro nlm_node_present() that can be used to check if a node is present
in a multi-chip configuration. This can be used even when NUMA is not enabled.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6272/
Yonghong Song [Sat, 21 Dec 2013 11:22:16 +0000 (16:52 +0530)]
MIPS: Netlogic: L1D cacheflush before thread enable on XLPII
On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/
Jayachandran C [Sat, 21 Dec 2013 11:22:15 +0000 (16:52 +0530)]
MIPS: Netlogic: Some cleanups for assembly code
No change in logic, the changes are:
* cleanup some whitespace and comments
* remove confusing argument of SYS_CPU_COHERENT_BASE macro
* make the numerical labels in macros consistent
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6273/
Jayachandran C [Sat, 21 Dec 2013 11:22:14 +0000 (16:52 +0530)]
MIPS: Netlogic: Add topology.h for XLP family
Add mach-netlogic/topology.h which contains XLP cpu number to core and
node mapping.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6271/
Jayachandran C [Sat, 21 Dec 2013 11:22:13 +0000 (16:52 +0530)]
MIPS: Netlogic: Add MSI support for XLP
Add MSI chip and MSIX chip definitions.
For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.
The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.
For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.
The MSI-X chip definition uses the standard functions to enable
and disable interrupts.
Signed-off-by: Jayachandran C <jchandra@broadcom.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
Deng-Cheng Zhu [Tue, 8 Oct 2013 17:33:53 +0000 (10:33 -0700)]
MIPS: malta: Incorporate PIIX4 ACPI I/O region in PCI controller resources
Boot log says:
pci 0000:00:0a.3: no compatible bridge window for [io 0x1000-0x103f]
pci 0000:00:0a.3: no compatible bridge window for [io 0x1100-0x110f]
The io resource starting point on Malta was modified by c5de50dada (MIPS:
Malta: Change start address to avoid conflicts.) to avoid conflicts with
ACPI and SMB devices. In fact, that was not needed (and now causing
southbridge ACPI missing) since 166c637075 (PCI: add pci_create_root_bus()
that accepts resource list) and 7c090e5bfa (mips/PCI: convert to
pci_scan_root_bus() for correct root bus resources) had already done the
correct fix.
This patch actually reverts the change made by c5de50dada. And with this
fix, log says:
pci 0000:00:0a.3: quirk: [io 0x1000-0x103f] claimed by PIIX4 ACPI
pci 0000:00:0a.3: quirk: [io 0x1100-0x110f] claimed by PIIX4 SMB
These things may not be used but as part of platform resources are better
off to be included.
Cc: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6037/
Apelete Seketeli [Thu, 19 Dec 2013 21:11:43 +0000 (22:11 +0100)]
MIPS: jz4740: update platform data for JZ4740 usb device controller
The platform data already available in tree for JZ4740 USB Device
Controller was previously used by an out-of-tree USB gadget driver
which was not relying on the musb driver and was written by Ingenic
and the Qi-Hardware community.
Update platform data for JZ4740 USB device controller to be used with
musb driver.
Eunbong Song [Wed, 27 Nov 2013 00:29:16 +0000 (00:29 +0000)]
MIPS: Kill CONFIG_MTD_PARTITIONS
This patch removes CONFIG_MTD_PARTITIONS in config files for MIPS.
Because CONFIG_MTD_PARTITIONS was removed by commit 6a8a98b22b10f1560d5f90aded4a54234b9b2724.
Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6162/ Signed-off-by: Eunbong Song <eunb.song@samsung.com>
Paul Burton [Tue, 19 Nov 2013 17:30:37 +0000 (17:30 +0000)]
MIPS: clean up resume declaration
This patch cleans up the declaration of the resume function by replacing
void pointers with their correct types. The irrelevant & incorrect
comment preceeding the resume function is replaced by one documenting
its function.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6146/
Steven J. Hill [Thu, 7 Nov 2013 12:48:29 +0000 (12:48 +0000)]
MIPS: microMIPS: mfhc1 & mthc1 support for the FPU emulator
This patch adds support for microMIPS encodings of the mfhc1 & mthc1
instructions introduced in release 2 of the mips32 & mips64
architectures, converting them to their mips32 equivalents for the FPU
emulator.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6110/
Rafał Miłecki [Thu, 12 Dec 2013 12:46:03 +0000 (13:46 +0100)]
bcma: gpio: add own IRQ domain
Input GPIO changes can generate interrupts, but we need kind of ACK for
them by changing IRQ polarity. This is required to stop hardware from
keep generating interrupts and generate another one on the next GPIO
state change.
This code allows using GPIOs with standard interrupts and add for
example GPIO buttons support.
Qais Yousef [Mon, 9 Dec 2013 09:49:45 +0000 (09:49 +0000)]
MIPS: include linux/types.h
The file uses u16 type but doesn't include its definition explicitly
I was getting this error when including this header in my driver:
arch/mips/include/asm/mipsregs.h:644:33: error: unknown type name ‘u16’
Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6212/
Qais Yousef [Fri, 6 Dec 2013 11:00:43 +0000 (11:00 +0000)]
MIPS: sead3: remove chosen node
The defaults are not always applicable and it makes it hard for the bootloader
to override them. By removing it we give the bootloader full control over what
command line parameters to pass.
Without this change we will need to modify the built-in dtb to add bootloader
cmd line parameters or do some work to append them after we unflatten the device
tree.
Sead3 is a development board, that's why we want to be able to change boot
parameters on the fly from the bootloader.
Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6208/
Update the early_printk code to include linux/serial_bcm63xx.h which
provides the definitions for the UART block registers. While at it,
remove the inclusion of serial_bcm63xx.h which was just there to allow
smooth transition.
Signed-off-by: Florian Fainelli <florian@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6203/
tty: serial: bcm63xx_uart: use linux/serial_bcm63xx.h
Now that the UART block defines have been moved to a separate file,
include that one and do not longer rely on the MIPS-specific
bcm63xx_regs.h header file.
Signed-off-by: Florian Fainelli <florian@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6204/
tty: serial: bcm63xx_uart: drop bcm_{readl,writel} macros
bcm_{readl,writel} macros expand to __raw_{readl,writel}, use these
directly such that we do not rely on the platform to provide these for
us. As a result, we no longer use bcm63xx_io.h, so remove that inclusion
too.
Signed-off-by: Florian Fainelli <florian@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6201/
Remove usage of -mno-jals compiler flag when building a pure
microMIPS kernel. The -mno-jals flag only ever existed within
Mentor toolchains. Dropping this flag allows all FSF toolchains
to work.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6200/
David Daney [Tue, 3 Dec 2013 19:46:51 +0000 (11:46 -0800)]
MIPS: OCTEON: Supply OCTEON+ USB nodes in internal device trees.
This will be needed by the next patch to use said nodes for probing
via the device tree.
Signed-off-by: David Daney <david.daney@cavium.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6185/
Paul Burton [Mon, 2 Dec 2013 16:48:38 +0000 (16:48 +0000)]
MIPS: Malta: use generic 8250 early console
This patch switches Malta from using the MIPS implementation of early
printk with Malta's prom_putchar to using the generic 8250_early
implementation. This offers a couple of advantages:
- We duplicate less generic code.
- The UART can be initialised rather than being reliant upon
inheriting a valid setup from the bootloader.
The Malta console_config function is extended to initialise the early
console if no earlycon= kernel parameter is provided, inheriting the
modetty0 bootloader environment if present and falling back to a
default 38400n8r setup if not. This matches the behaviour used for the
regular console= parameter.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6183/
Paul Burton [Mon, 2 Dec 2013 16:48:37 +0000 (16:48 +0000)]
MIPS: Malta: mux & enable SERIRQ interrupt
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ
pin of the PIIX4 and to enable that interrupt. The kernel depends upon
the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but
previously would not configure it, instead relying upon the bootloader
having done so. If that is not the case then the typical result is that
the system appears to hang once it reaches userland as no output is
displayed on the UART.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6182/
Paul Burton [Mon, 2 Dec 2013 16:48:36 +0000 (16:48 +0000)]
MIPS: Malta: initialise the RTC at boot
The RTC is used on Malta to estimate the clock frequency of the CPU &
optionally the GIC. However the kernel previously did not initialise the
RTC, instead relying upon the bootloader having done so. In order to
minimise dependencies which the kernel has upon the bootloader this
patch causes the kernel to initialise the RTC itself prior to making use
of it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6184/
Paul Burton [Fri, 29 Nov 2013 17:07:13 +0000 (17:07 +0000)]
MIPS: Malta: remove unused cpu_khz variable
This variable was introduced by commit 96348c8f (of Ralf's historic
Linux/MIPS repository) "Remaining fixes for MIPS's eval boards." but
I don't see any use of it either then or now. Remove it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6171/
Aaro Koskinen [Wed, 27 Nov 2013 22:11:44 +0000 (00:11 +0200)]
MIPS: cavium-octeon: export symbols needed by octeon-ethernet
Export symbols needed by the octeon-ethernet driver. The patch fixes a
build failure with CONFIG_OCTEON_ETHERNET=m.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6166/
Guenter Roeck [Mon, 25 Nov 2013 23:21:00 +0000 (15:21 -0800)]
MIPS: Fix build error seen in some configurations
The following build error is seen if CONFIG_32BIT is undefined,
CONFIG_64BIT is defined, and CONFIG_MIPS32_O32 is undefined.
asm/syscall.h: In function 'mips_get_syscall_arg':
arch/mips/include/asm/syscall.h:32:16: error: unused variable 'usp' [-Werror=unused-variable]
cc1: all warnings being treated as errors
Fixes: c0ff3c53d4f9 ('MIPS: Enable HAVE_ARCH_TRACEHOOK') Signed-off-by: Guenter Roeck <linux@roeck-us.net> Acked-by: David Daney <david.daney@cavium.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6160/
Aaro Koskinen [Fri, 1 Nov 2013 15:06:04 +0000 (17:06 +0200)]
MIPS: cavium-octeon: fix early boot hang on EBH5600 board
The boot hangs early on EBH5600 board when octeon_fdt_pip_iface() is
trying enumerate a non-existant interface. The actual hang happens in
cvmx_helper_interface_get_mode():
when interface == 4. We can avoid this situation by first checking that
the interface exists in the DTB.
Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Acked-by: David Daney <david.daney@cavium.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6101/
When booting with in-kernel DTBs, the pruning code will enumerate
interfaces 0-4. However, there is memory reserved only for 4 so some
other data will get overwritten by cvmx_helper_interface_enumerate().
Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Acked-by: David Daney <david.daney@cavium.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6102/
Felix Fietkau [Fri, 27 Sep 2013 12:41:45 +0000 (14:41 +0200)]
MIPS: partially inline dma ops
Several DMA ops are no-op on many platforms, and the indirection through
the mips_dma_map_ops function table is causing the compiler to emit
unnecessary code.
Inlining visibly improves network performance in my tests (on a 24Kc
based system), and also slightly reduces code size of a few drivers.
coherentio is changed from EXPORT_SYMBOL_GPL to EXPORT_SYMBOL, because
it is now potentially being accessed by any driver using the DMA mapping
API.
Signed-off-by: Felix Fietkau <nbd@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5913/
Felix Fietkau [Fri, 27 Sep 2013 12:41:44 +0000 (14:41 +0200)]
MIPS: improve checks for noncoherent DMA
Only one MIPS development board actually supports enabling/disabling DMA
coherency at runtime, so it's not a good idea to push the overhead of
checking that configuration setting onto every other supported target as
well.
Signed-off-by: Felix Fietkau <nbd@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5912/
Steven J. Hill [Wed, 1 Jan 2014 15:35:32 +0000 (16:35 +0100)]
MIPS: APRP: Code formatting clean-ups.
Clean-up code according to the 'checkpatch.pl' script.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/6097/ Reviewed-by: John Crispin <blogic@openwrt.org>
Deng-Cheng Zhu [Wed, 30 Oct 2013 20:52:10 +0000 (15:52 -0500)]
MIPS: APRP: Add support for Malta CMP platform.
Malta with multi-core CM platforms can now use APRP functionality.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6096/
Deng-Cheng Zhu [Wed, 1 Jan 2014 15:29:03 +0000 (16:29 +0100)]
MIPS: APRP: Add RTLX API support for CMP platforms.
This patch adds RTLX API support for platforms having a CMP.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/6095/ Reviewed-by: John Crispin <blogic@openwrt.org>
Deng-Cheng Zhu [Wed, 1 Jan 2014 15:26:46 +0000 (16:26 +0100)]
MIPS: APRP: Split RTLX support into separate files.
Split the RTLX functionality in preparation for adding support for CMP
platforms. Common functions remain in the original file and a new file
contains code specific to platforms that do not have a CMP.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/6093/ Reviewed-by: John Crispin <blogic@openwrt.org>
Deng-Cheng Zhu [Wed, 30 Oct 2013 20:52:07 +0000 (15:52 -0500)]
MIPS: APRP: Add VPE loader support for CMP platforms.
This patch adds VPE loader support for platforms having a CMP.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6092/
Deng-Cheng Zhu [Wed, 30 Oct 2013 20:52:06 +0000 (15:52 -0500)]
MIPS: APRP: Split VPE loader into separate files.
Split the VPE functionality in preparation for adding support
for CMP platforms. Common functions remain in the original file
and a new file contains code specific to platforms that do not
have a CMP present.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6094/
Steven J. Hill [Fri, 4 Oct 2013 21:23:28 +0000 (16:23 -0500)]
MIPS: Clean up MIPS MT and CMP configuration options.
This patch accomplishes the following:
* Clean up wording on all MIPS MT configuration menu items.
* Simplify and neaten up options selected by MIPS_MT_SMP.
* Make MIPS_MT_SMTC support as deprecated.
* Make MIPS_CMP support to depend on MIPS_MT_SMP also.
* Remove redundant options selected by MIPS_CMP.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6019/
Leonid Yegoshin [Wed, 27 Nov 2013 10:07:53 +0000 (10:07 +0000)]
MIPS: Add support for interAptiv cores
The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6163/
Steven J. Hill [Thu, 14 Nov 2013 16:12:32 +0000 (16:12 +0000)]
MIPS: Add debugfs file to print the segmentation control registers
Add a new mips/segments debugfs file to print the 6 segmentation
control registers for supported cores. A sample from a proAptiv core
is given below:
Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6137/
Segment Virtual Size Access Mode Physical Caching EU
------- ------- ---- ----------- -------- ------- --
0 e0000000 512M MK UND U 0
1 c0000000 512M MSK UND U 0
2 a0000000 512M UK 000 2 0
3 80000000 512M UK 000 3 0
4 40000000 1G MUSK UND U 1
5 00000000 1G MUSK UND U 1
Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Thu, 14 Nov 2013 16:12:31 +0000 (16:12 +0000)]
MIPS: Add support for FTLBs
The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its
purpose is to reduce the number of TLB misses by increasing the effective
TLB size and keep the implementation complexity to minimum levels.
A supported core can have both VTLB and FTLB.
Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6139/
Leonid Yegoshin [Thu, 14 Nov 2013 16:12:27 +0000 (16:12 +0000)]
MIPS: Add support for the proAptiv cores
The proAptiv Multiprocessing System is a power efficient multi-core
microprocessor for use in system-on-chip (SoC) applications.
The proAptiv Multiprocessing System combines a deep pipeline
with multi-issue out of order execution for improved computational
throughput. The proAptiv Multiprocessing System can contain one to
six MIPS32r3 proAptiv cores, system level coherence
manager with L2 cache, optional coherent I/O port, and optional
floating point unit.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6134/
Leonid Yegoshin [Thu, 14 Nov 2013 16:12:25 +0000 (16:12 +0000)]
MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLB
For MIPS32R3 supported cores, the EHINV bit needs to be set when
invalidating the TLB. This is necessary because the legacy software
method of representing an invalid TLB entry using an unmapped address
value is not guaranteed to work.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6132/
Steven J. Hill [Thu, 14 Nov 2013 16:12:24 +0000 (16:12 +0000)]
MIPS: features: Add initial support for Segmentation Control registers
MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
fixed the IRQ number for the ttyS2 CBUS UART. However, this now
conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta
interrupt code arbitrarily binds IPIs to INT2 and INT3 and since
ttyS2 uses the INT2 IRQ line, closing the device disables the
INT2 interrupt and this effectively disables the IPI1 interrupt
as well. This patch is mainly a workaround until the Malta code
is fixed properly.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6045/
Steven J. Hill [Wed, 9 Oct 2013 15:47:23 +0000 (16:47 +0100)]
MIPS: GIC: Send IPIs using the GIC
If GIC is present, then use it to send IPIs between the cores.
Using GIC for IPIs is simpler and is usable for multicore
systems compared to the existing way of doing IPIs where all VPEs
had to be disabled for another VPE to access the Cause register
in one of the TCs and enable all the VPEs back.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6040/
Markos Chandras [Wed, 9 Oct 2013 15:16:25 +0000 (16:16 +0100)]
MIPS: MT: Mark existing TCs as present
According to Documentation/cpu-hotplug.txt, the cpu_present_mask should
contain all the CPUs which are present in the system. Therefore, all the TCs
currently present in the system should be marked as 'present' even if they
will never be brought online.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6039/
MIPS: mm: c-r4k: Panic if IL or DL fields have a reserved value
According to MIPS32 and MIPS64 PRA documents,
a value of 7 in IL and DL fields is marked as "Reserved"
so panic if the core uses this value in the config1 register.
Also simplify the code a little bit.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5861/
Ilia Mirkin [Fri, 6 Dec 2013 23:56:53 +0000 (18:56 -0500)]
MIPS: BCM47XX: Fix some very confused types and data corruption
Fix nvram_read_alpha2 copying too many bytes over the ssb_sprom
structure. Also fix the arguments of the read_macaddr, although the code
was technically not wrong before due to an extra dereference.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6211/
Hauke Mehrtens [Sun, 22 Dec 2013 13:36:31 +0000 (14:36 +0100)]
MIPS: BCM47XX: add cpu-feature-overrides.h
The BCM47XX SoC code missed a cpu-feature-overrides.h header file, this
patch adds it. This code supports a long line of SoCs with different
features so for some features we still have to rely on the runtime
detection.
This was crated by checking the features of a BCM4712, BCM4704,
BCM5354, BCM4716 and BCM4706 SoC and then tested on these SoCs. There
are some SoCs missing but I hope they do not have any more or less
features.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6289/
The defconfig for bcm47xx contained lots of driver which are not
special for these SoCs and missed on the other side some some drivers
for parts essential for these SoC and only found on here. The flash,
usb and some Ethernet driver were missing.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5930/
The BCM47xx SoCs have a 8250 serial compatible console at address
0x18000300 and an other at 0x18000400. On most devices 0x18000300 is
wired to some pins on the board, we should use that.
This is the smae for the AI (bcma) and the SB (ssb) bus, this is some
offset on the chip common core.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5889/
projects / karo-tx-linux.git / log