Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "
Recommended workaround is as follows:
Do both of the following:
1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.
For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:
3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.
Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.
Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
ARM: cache: implement a default weak flush_cache() function
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.
In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.
So in this patch remove such code in flush_cache() and only call
flush_dcache_range().
ARM: cache: add an empty stub function for invalidate/flush dcache
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.
To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
Correct License and Copyright information on few files
gpio.h - Added missing copyright in few files.
rsa-mod-exp.h - Corrected copyright in the file.
fsl_sec.h - Added missing license in files
drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license
The menuconfig for drivers are getting more and more cluttered
and unreadable because too many entries are displayed in a single
flat menu. Use hierarchic menu for each category.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
Alexander Stein [Fri, 24 Jul 2015 07:22:15 +0000 (09:22 +0200)]
arm/rpi: Enable dcache
Now that mailbox driver supports cache flush and invalidation, we can
enable dcache.
Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Alexander Stein [Fri, 24 Jul 2015 07:22:14 +0000 (09:22 +0200)]
dwc2: Add dcache support
This adds dcache support for dwc2. The DMA buffers must be DMA aligned and
is flushed for outgoing transactions before starting transfer. For
ingoing transactions it is invalidated after the transfer has finished.
Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Update to apply again on top of DM patches] Signed-off-by: Tom Rini <trini@konsulko.com>
Alexander Stein [Fri, 24 Jul 2015 07:22:13 +0000 (09:22 +0200)]
arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox
When using dcache the setup data for the mailbox must be actually written
into memory before calling into firmware. Thus flush and invalidate the
memory.
Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Alexander Stein [Fri, 24 Jul 2015 07:22:12 +0000 (09:22 +0200)]
ARM: bcm283x: Allocate all mailbox buffers cacheline aligned
The mailbox buffer is required to be at least 16 bytes aligned, but for
cache invalidation and/or flush it needs to be cacheline aligned.
Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations.
Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Alexander Stein [Fri, 24 Jul 2015 07:22:11 +0000 (09:22 +0200)]
ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.
Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Alexander Stein [Fri, 24 Jul 2015 07:22:10 +0000 (09:22 +0200)]
arm1136/arm1176: Merge cache handling code
As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.
Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Add hunk to arch/arm/cpu/arm1136/Makefile] Signed-off-by: Tom Rini <trini@konsulko.com>
Alexander Stein [Fri, 24 Jul 2015 07:22:09 +0000 (09:22 +0200)]
arm1136: Remove dead code
Apparently lcd_panel_disable is not defined anywhere, so no config for
an arm1136 board would have set CONFIG_LCD. Remove the unused code.
Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
sniper: Keypad support, with recovery and fastboot key combinations
Using the twl4030 keypad allows booting directly into some special boot modes,
such as recovery or fastboot. the VOL+ key will trigger a boot to recovery while
the VOL- key will trigger a boot to fastboot.
The G (gesture) key remains unused at this point.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
sniper: Power off when the power on reason is not a valid one
In most cases, userspace will attempt to power off the device with HALT instead
of POWER_OFF, which triggers a reset instead of a proper power off from the
TWL4030. Hence, it is up to the bootloader to actually turn the device off when
there is no reason to turn it on.
A reboot identified with the OMAP reboot mode bits set is acceptable, as well as
a power on reason from either the power button, USB or charger plug.
Other cases should trigger a power off. Note that for the U-Boot reset command
to take effect, we have to fill-in the OMAP reboot bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support for the fastboot USB gadget, including flashing to the
internal MMC and reboot to bootloader or not.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Update to use Kconfig for MUSB] Signed-off-by: Tom Rini <trini@konsulko.com>
Now that the serial number is correctly defined, we can pass it to the kernel
using the (legacy) ATAG method. It will be automatically passed via device-tree
when enabled.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
sniper: Serial number support, obtained from die ID
The OMAP3 has some die-specific ID bits that we can use to give the device a
(more or less) unique serial number. This is particularly useful for e.g. USB.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for the omap3 reboot mode mechanism and exports the reboot
mode via an environment variable, that is used in the boot command to make it
possible to boot from the recovery partition.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
The LG Optimus Black (P970) codename sniper is a smartphone that was designed
and manufactured by LG Electronics (LGE) and released back in 2011.
It is using an OMAP3630 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up. This port is aimed at running an Android version
such as Replicant, the fully free Android distribution. However, support for
upstream Linux with device-tree and common GNU/Linux distros boot commands
could be added in the future.
For more information about the journey to freeing this device, please read the
series of blog posts at:
http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add CONFIG_OF_SUPPORT] Signed-off-by: Tom Rini <trini@konsulko.com>
Reboot mode is written in scratchpad memory before reboot in the form of a
single char, that is the first letter of the reboot mode string as passed to the
reboot function.
This mechanism is supported on OMAP3 both my the upstream kernel and by various
TI kernels.
It is up to each board to make use of this mechanism or not.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
input: TWL4030 input support for power button, USB and charger
This adds support for detecting a few inputs exported by the TWL4030.
Currently-supported inputs are the power button, USB and charger presence. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for powering off (the omap3 SoC) from the twl4030. This is
especially useful when the kernel does not actually power off the device using
this method but reboots and leaves it up to the bootloader to actually turn the
power off. Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The change adds SPL build support to Timll DevKit3250 board, the
generated SPL image can be uploaded over UART5, JTAG or stored on
NAND. SPL is designed to load U-boot image from NAND.
All new NAND chip defines in board configuration are needed by
SPL NAND "simple" framework, the framework is used to reduce
potentially duplicated code from LPC32xx SLC NAND driver.
lpc32xx: devkit3250: update of board configuration
This change adds more peripherals to Timll DevKit3250 board, namely
MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.
Also the default serial console is changed to UART5, added an option
to pass device tree blob by means of bootm, predefined environment
variables are slightly extended and reserved space on NAND to store
user defined U-boot environment.
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
spl: nand: simple: replace readb() with chip specific read_buf()
Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.
NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
Rob Herring [Fri, 17 Jul 2015 15:57:17 +0000 (10:57 -0500)]
image: fix Android ramdisk support when dtb is specified
If a dtb is specified on the command-line, the Android boot image ramdisk
will not be found. Fix this so that we can specify the ramdisk address and
dtb address. The syntax is to enter the Android boot image address for
both the kernel and ramdisk.
Mark Tomlinson [Wed, 1 Jul 2015 04:38:29 +0000 (16:38 +1200)]
JFFS2: Use merge sort when parsing filesystem
When building the file system the existing code does an insertion into
a linked list. It attempts to speed this up by keeping a pointer to
where the last entry was inserted but it's still slow.
Now the nodes are just inserted into the list without searching
through for the correct place. This unsorted list is then sorted once
using mergesort after all the entries have been added to the list.
This speeds up the scanning of the flash file system considerably.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Mark Tomlinson [Wed, 1 Jul 2015 04:38:28 +0000 (16:38 +1200)]
JFFS2: Use CLEANMARKER to reduce scanning time
If a sector has a CLEANMARKER at the beginning, it indicates that the
entire sector has been erased. Therefore, if this is found, we can skip the
entire block. This was not being done before this patch.
The code now does the same as the kernel does when encountering a
CLEANMARKER. It still checks that the next few words are FFFFFFFF, and if
so, the block is assumed to be empty, and so is skipped.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Mark Tomlinson [Wed, 1 Jul 2015 04:38:27 +0000 (16:38 +1200)]
JFFS2: Change scansize to match linux kernel
The scan code is similar to the linux kernel, but the kernel defines a much
smaller size to scan through before deciding a sector is blank. Assuming
that what is in the kernel is OK, make these two match.
On its own, this change makes no difference to scanning of any sectors
which have a clean marker at the beginning, since the entire sector is not
blank.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Mark Tomlinson [Wed, 1 Jul 2015 04:38:25 +0000 (16:38 +1200)]
JFFS2: Improve speed reading flash files
jffs2_1pass_read_inode() would read the entire data for each node
in the filesystem, regardless of whether it was part of the file
to be loaded or not. By only reading the header data for an inode,
and then reading the data only when it is found to be part of the
file to be loaded, much copying of data is saved.
jffs2_1pass_list_inodes() read each inode for every file in the
directory into a buffer. By using NULL as a buffer pointer, NOR
flash simply returns a pointer, and therefore avoids a memory copy.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Mark Tomlinson [Wed, 1 Jul 2015 04:38:24 +0000 (16:38 +1200)]
JFFS2: Only list each directory entry once
If multiple versions of a file exist, only the most recent version
should be used. The scheme to write 0 for the inode in older versions
did not work, since this would have required writing to flash.
The only time this caused an issue was listing a directory, where older
versions of the file would still be seen. Since the directory entries
are sorted, just look at the next entry in the list, and if it's the same
move to that entry instead.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Mark Tomlinson [Wed, 1 Jul 2015 04:38:23 +0000 (16:38 +1200)]
JFFS2: Speed up and fix comparison functions
Copying complete nodes from flash can be slow if the flash is slow
to read. By only reading the data needed, the sorting operation can
be made much faster.
The directory entry comparison function also had a two bugs. First, it
did not ensure the name was copied, so the name comparison may have
been faulty (although it would have worked with NOR flash). Second,
setting the ino to zero to ignore the entry did not work, since this
was either writing to a temporary buffer, or (for NOR flash) directly
to flash. Either way, the change was not remembered.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Mark Tomlinson [Wed, 1 Jul 2015 04:38:22 +0000 (16:38 +1200)]
JFFS2: Return early when file read not necessary
If a destination is not provided, jffs2_1pass_read_inode() only
returns the length of the file. In this case, avoid reading all
the data nodes, and return as soon as the length of the file is
known.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Heiko Schocher [Mon, 29 Jun 2015 07:10:48 +0000 (09:10 +0200)]
arm, at91: support for sam9260 based smartweb board
add support for the at91sam9260 based board smartweb from
siemens. SPL is used without serial support, as this
SoC has only 4k sram for running SPL. Here a U-Boot
bootlog:
Stefan Roese [Tue, 11 Aug 2015 15:12:44 +0000 (17:12 +0200)]
net: e1000: Increase autoneg timeout to 8 seconds
The current 4.5 timeout for the autonegotiation are not enough to
complete it on my platform. Using the Intel E1000 PCIe card in the
Marvell db-mv784mp-gp eval board. So lets increase the timeout to
8 seconds.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Simon Glass <sjg@chromium.org>
CONFIG_TFTP_TSIZE should limit a tftp downloads progress to 50 '#'
chars. Make this work also for small files.
If the file size is small, i.e. smaller than 2 tftp block sizes the
number of '#' can get much larger. i.e. with a 1 byte file 65000
characters are printed, with a 512 byte file around 500.
When using CONFIG TFTP BLOCKSIZE together with CONFIG_IP_DEFRAG the
issue is more notable.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Rob Herring [Sat, 20 Jun 2015 23:29:55 +0000 (00:29 +0100)]
ARM: highbank: remove DRAM bank setup
On the highbank platform the SoC's management controller firmware
will probe the DRAM modules and populates the initial device tree with
the correct values. Therefore the memory sizes in the DT are already
correct, so remove U-Boot's DRAM bank setup so the memory node is not
"fixed up" by u-boot.
Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
Peng Fan [Fri, 7 Aug 2015 08:43:46 +0000 (16:43 +0800)]
fsl: common: pfuze: no use original pfuze code if DM_PMIC
If enable DM PMIC and REGULATOR, we should not use original power
framework. So need to comment out the pfuze code for original power
framework, when CONFIG_DM_PMIC_PFUZE100 defined.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Peng Fan [Fri, 7 Aug 2015 08:43:45 +0000 (16:43 +0800)]
power: regulator: add pfuze100 support
1. Add new regulator driver pfuze100.
* Introduce struct pfuze100_regulator_desc for maintaining info
for one regulator.
2. Add new Kconfig entry DM_REGULATOR_PFUZE100 for pfuze100.
3. This driver intends to support PF100, PF200 and PF3000.
4. Add related macro definition in pfuze header file.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org>
Peng Fan [Fri, 7 Aug 2015 08:43:44 +0000 (16:43 +0800)]
power: pmic: pfuze100 support driver model
1. Support driver model for pfuze100.
2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100
3. This driver intends to support PF100, PF200 and PF3000, so add
the device id into the udevice_id array.
4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Peng Fan [Fri, 7 Aug 2015 08:43:43 +0000 (16:43 +0800)]
power: regulator: update comments for regulator-name
We do not need that "regulator-name" property must be provided in dts.
If "regulator-name" property is not provided in dts, node name
will chosen for settings '.name' field of uc_pdata.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org>
Peng Fan [Fri, 7 Aug 2015 08:43:41 +0000 (16:43 +0800)]
power: pfuze100 correct SWBST macro definition
According to datasheet, SWBST_MODE starts from bit 2 and it occupies 2 bits.
So SWBST_MODE_MASK should be 0xC, and SWBST_MODE_xx should be ([mode] << 2).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
net: phy: delay only if reset handler is registered
With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only
reset if a reset handler is registered. If there is no reset handler there
is no need to wait for a device to come out of the reset.
qoriq eth.c bugfix: handle received corrupted frames correctly
The rxbd is not correctly handled in case of a frame physical error
(FPE) or frame size error (FSE). The rxbd must be cleared and
advanced in case of an error to avoid receive stall.
Signed-off-by: Daniel Inderbitzin <daniel.inderbitzin@gmail.com>
LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.
It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.
Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
net: lpc32xx: improve MAC configuration on reset and initialization
This change rearranges general MAC configuration and PHY specific
configuration of MAC registers (duplex mode and speed), before this
change set bits related to PHY configuration in MAC2 and COMMAND
registers are rewritten by the following writing to the registers.
Without the change auto negotiation on boot quite often is not
completed in reasonable time:
Waiting for PHY auto negotiation to complete......... TIMEOUT !
Additionally MAC1_SOFT_RESET clear bit is removed since it is done in
preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead
added missing MCFG_RESET_MII_MGMT on device initialization.
net: lpc32xx: connect MAC to phy with CONFIG_PHY_ADDR id
The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX
MAC to some specified phy by phy id, by chance the single user of
lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may
have non-zero CONFIG_PHY_ADDR value, fix it.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: lpc32xx: correct command register reset value
According to LPC32x0 User Manual the following bits in Command
register 0x3106_0100 are defined:
Bit Symbol
2 - Unused
3 RegReset
4 TxReset
5 RxReset
Fix wrong (1-bit shifted right) COMMAND_RESETS value, which sets
an unused bit, but neglects RxReset.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tearing down an unitialized rx channel causes a pending address hole
event to be queued. When booting linux it will report this pending
as something like "Address Hole seen by USB_OTG at address 57fff584",
since u-boot did not handled this interrupt. Prevent that by not
tearing down the rx channel, when not receiving.
Support the 88E1510 PHY which is very similar to the 88E1518.
I also set the INTn output and configured the LEDs.
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Clemens Gruber [Sat, 6 Jun 2015 12:44:57 +0000 (14:44 +0200)]
net: Improve 88E151x PHY initialization
- The EEE fixup magic should also be enabled for RGMII
- Improved comments
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tim Harvey [Tue, 19 May 2015 17:01:20 +0000 (10:01 -0700)]
e1000: remove unnecessary clearing of SWSM.SWSM_SMBI
remove unnecessary clearing of SWSM.SWSM_SMBI when obtaining the SW
semaphore. This was introduced in 951860634fdb557bbb58e0f99215391bc0c29779
while adding i210 support and should be now resolved by releasing the
semaphore when no longer needed.
Cc: Marcel Ziswiler <marcel@ziswiler.com> Cc: Marek Vasut <marex@denx.de> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tim Harvey [Tue, 19 May 2015 17:01:18 +0000 (10:01 -0700)]
e1000: releasing semaphore once no longer needed
Once the hwsw semaphore is acquired, it must be released when access to the
hw is completed. Without this subsequent calls to acquire will timeout
obtaining the semaphore.
Cc: Marcel Ziswiler <marcel@ziswiler.com> Cc: Marek Vasut <marex@denx.de> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marek Vasut [Mon, 27 Jul 2015 20:39:38 +0000 (22:39 +0200)]
mmc: dw_mmc: Improve handling of data transfer failure
In case the data transfer failure happens, instead of returning
immediatelly, make sure the DMA is disabled, status register is
cleared and the bounce buffer is stopped.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Mon, 27 Jul 2015 20:39:36 +0000 (22:39 +0200)]
mmc: dw_mmc: Stop bounce buffer even in case of failure
The driver didn't stop the bounce buffer in case a data transfer
failed. This would lead to memory leakage if the communication
between the CPU and the card is unreliable. Add the missing call
to stop the bounce buffer.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
Hans de Goede [Sat, 8 Aug 2015 15:45:18 +0000 (17:45 +0200)]
dm: serial: Add a REQUIRE_SERIAL_CONSOLE option for boards with no serial port
Currently the serial code assumes that there is always at least one serial
port (and panics / crashes due to null pointer dereferences when there is
none).
This makes it impossible to use u-boot on boards where there is no (debug)
serial port, because e.g. all uart pins are muxed to another function.
This commit adds a CONFIG_REQUIRE_SERIAL_CONSOLE Kconfig option, which
defaults to y (preserving existing behavior), which can be set to n on
such boards to make them work.
This commit only implements this for CONFIG_DM_SERIAL=y configs, as allowing
running without a serial port for CONFIG_DM_SERIAL=n configs is non trivial,
and is not necessary at this moment.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
Hans de Goede [Mon, 3 Aug 2015 17:45:37 +0000 (19:45 +0200)]
sunxi: display: Add a few extra register and constant defines
Add a few extra sunxi display registers and constant defines.
Also rename some existing defines (e.g. dropping _GCTRL) and make
some more generic (e.g. dropping the 2x scaling from
SUNXI_LCDC_TCON1_TIMING_V_TOTAL).
This is a preparation patch for adding composite video out support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 3 Aug 2015 21:01:38 +0000 (23:01 +0200)]
sunxi: display: Replace #ifdef-ery with helper functions
All the #ifdef-ery in selecting the default and fallback monitor type is
becoming unyielding and makes the code hard to read, replace it with a few
helper functions.
This will also be useful with the upcoming CHIP board which has display
adapter daughterboards which should be runtime detectable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 1 Aug 2015 12:44:29 +0000 (14:44 +0200)]
sunxi: Do not add a stdout-path alias to dts on boards without a serial port
Do not add a bogus (pointing to a non existing serial port) stdout-path
alias to dts on boards without a serial port.
Note that we still define CONS_INDEX as this is used by the SPL where we do
not use DM_SERIAL and thus CONFIG_REQUIRE_SERIAL_CONSOLE is not honored.
We are getting away with this because the sun5i die actually has
an uart0, which in the A13 package is not routed to the outside,
so we are simply sending SPL bootup messages to the tx pin at the
edge of the die, and they go no further from there...
And sofar we only have one A13 board which does not have a serial
port, all others do have a serial port. This kinda makes sense since
the A13 is a much lower pincount package compared to all the other
sunxi SoCs.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Wed, 8 Jul 2015 14:44:22 +0000 (16:44 +0200)]
sunxi: usb-phy: Never power off the usb ports
USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.
Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.
This patch removes the powering off calls, fixing the undesirable power
bouncing.
Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Piotr Zierhoffer [Thu, 23 Jul 2015 12:33:03 +0000 (14:33 +0200)]
sunxi: nand: Add board configuration options
When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.
This commit also introduces the configurable options in Kconfig.
Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Piotr Zierhoffer [Thu, 23 Jul 2015 12:33:02 +0000 (14:33 +0200)]
sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support
This driver adds NAND support to SPL.
It was tested on Allwinner A20.
Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Karol Gugala [Thu, 23 Jul 2015 12:33:01 +0000 (14:33 +0200)]
sunxi: nand: Add pinmux and clock settings for NAND support
To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.
Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Dinh Nguyen [Sat, 1 Aug 2015 01:42:10 +0000 (03:42 +0200)]
arm: socfpga: misc: Add support for printing FPGA type
Add code which uses the new functions for obtaining FPGA ID from
the scan manager. This new code prints the FPGA model attached to
the SoCFPGA during boot and sets environment variable "fpgatype",
which can be used to determine the FPGA model in U-Boot scripts.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de>
projects / karo-tx-uboot.git / log