Brian Norris [Sat, 10 Aug 2013 08:09:49 +0000 (01:09 -0700)]
mtd: nand: stop exporting nand_default_bbt
I removed the last non-nand_base users of this, and we shouldn't have
any more modules that need to access it. It's only non-static to share
between nand_base and nand_bbt.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Brian Norris [Wed, 31 Jul 2013 00:53:00 +0000 (17:53 -0700)]
mtd: nand: remove NAND_BBT_SCANEMPTY
NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its
single remaining user.
NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway,
omap2 doesn't scan the chip for bad blocks (courtesy of
NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant.
nand_base.c shouldn't have to know the implementation details of
nand_bbt's in-memory BBT. Specifically, nand_base shouldn't perform the
bit masking and shifting to isolate a BBT entry.
Instead, just move some of the BBT code into a new nand_markbad_bbt()
interface. This interface allows external users (i.e., nand_base) to
mark a single block as bad in the BBT. Then nand_bbt will take care of
modifying the in-memory BBT and updating the flash-based BBT (if
applicable).
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
/*
* Note that numblocks is 2 * (real numblocks) here, see i+=2
* below as it makes shifting and masking less painful
*/
I don't think it ever could have been "less painful" to have to shift an
extra bit (or 2, or 3) at various points in nand_bbt.c (and even
outside, since we leak our in-memory format). But now it is certainly
more painful, since we have nice macros and functions to retrieve the
relevant portions of the BBT.
This patch removes any points where the block number is
doubled/halved/otherwise-shifted, instead representing the block number
in its most natural form: as the actual block number.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Brian Norris [Wed, 31 Jul 2013 00:52:55 +0000 (17:52 -0700)]
mtd: nand: add accessors, macros for in-memory BBT
There is an abundance of magic numbers and complicated shifting/masking
logic in the in-memory BBT code which makes the code unnecessary complex
and hard to read.
This patch adds macros to represent the 00b, 01b, 10b, and 11b
memory-BBT magic numbers, as well as two accessor functions for reading
and marking the memory-BBT bitfield for a given block.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Huang Shijie [Tue, 27 Aug 2013 09:29:07 +0000 (17:29 +0800)]
mtd: gpmi: imx6: fix the wrong method for checking ready/busy
In the imx6, all the ready/busy pins are binding togeter.
So we should always check the ready/busy pin of the chip 0.
In the other word, when the CS1 is enabled, we should also check the
ready/busy of chip 0; if we check the ready/busy of chip 1,
we will get the wrong result.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
David Woodhouse [Fri, 25 Oct 2013 14:03:59 +0000 (15:03 +0100)]
mtd: gpmi: fix ECC regression
The "legacy" ECC layout used until 3.12-rc1 uses all the OOB area by
computing the ECC strength and ECC step size ourselves.
Commit 2febcdf84b ("mtd: gpmi: set the BCHs geometry with the ecc info")
makes the driver use the ECC info (ECC strength and ECC step size)
provided by the MTD code, and creates a different NAND ECC layout
for the BCH, and use the new ECC layout. This causes a regression:
We can not mount the ubifs which was created by the old NAND ECC layout.
This patch fixes this issue by reverting to the legacy ECC layout.
We will probably introduce a new device-tree property to indicate that
the new ECC layout can be used. For now though, for the imminent 3.12
release, we just unconditionally revert to the 3.11 behaviour.
This leaves a harmless cosmetic warning about an unused function. At
this point in the cycle I really don't care.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Huang Shijie <b32955@freescale.com>
Huang Shijie [Fri, 16 Aug 2013 02:10:08 +0000 (10:10 +0800)]
mtd: gpmi: remove the nand_scan()
In order to make the nand_scan() work, the current code uses the hack code
to init the @nand_chip->ecc.size and the @nand_chip->ecc.strength. and
re-init some the ECC info in the gpmi_pre_bbt_scan().
This code is really a little ugly.
The patch does following changes:
(1) Use the nand_scan_ident()/nand_scan_tail() to replace the nand_scan().
(2) Init all the necessary values in the gpmi_init_last()
before we call the nand_scan_tail().
(3) remove the code setting the ECC info, let the mtd layer to do the
real job.
(4) remove the gpmi_scan_bbt(). we do not need this function any more.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Huang Shijie [Fri, 17 May 2013 03:17:34 +0000 (11:17 +0800)]
mtd: gpmi: set the BCH's geometry with the ecc info
If the nand chip provides us the ECC info, we can use it firstly.
The set_geometry_by_ecc_info() will use the ECC info, and
calculate the parameters we need.
Rename the old code to legacy_set_geometry() which will takes effect
when there is no ECC info from the nand chip or we fails in the ECC info case.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Brian Norris [Wed, 31 Jul 2013 00:52:58 +0000 (17:52 -0700)]
mtd: nand: refactor chip->block_markbad interface
The chip->block_markbad pointer should really only be responsible for
writing a bad block marker for new bad blocks. It should not take care
of BBT-related functionality, nor should it handle bookkeeping of bad
block stats.
This patch refactors the 3 users of the block_markbad interface (plus
the default nand_base implementation) so that the common code is kept in
nand_block_markbad_lowlevel(). It removes some inconsistencies between
the various implementations and should allow for more centralized
improvements in the future.
Because gpmi-nand no longer needs the nand_update_bbt() function, let's
stop exporting it as well.
Wolfram Sang [Wed, 10 Jul 2013 15:57:41 +0000 (16:57 +0100)]
mtd: gpmi-nand: don't use devm_pinctrl_get_select_default() in probe
Since commit ab78029 (drivers/pinctrl: grab default handles from device core),
we can rely on device core for setting the default pins. Compile tested only.
Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d0631001288a5974afc0b2a5f568bcdecb4d
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Luwei Zhou [Wed, 30 Oct 2013 06:24:34 +0000 (14:24 +0800)]
ENGR00285441 mxc: mlb: Fix the receive issue of ISOC mode on Sabreauto
This patch fixes the receive issue of MLB ISO mode on Sabreauto side.
During debug, it is found that the Sabreauto can only receive
1/5 packets of MITB sends.The MITB sends out 188 bytes per packet.
The Sabreauto receives 188*5 bytes. It seems that the packet length
on Sabreauto side is 5 times larger than MITB side. After changing
the defautl block number to 1, Sabreauto passes the test.
- Configure boot partition
Expose the interfaces that used to enable the configurations
of the boot mode of the eMMC cards.
usage how-to and examples:
Enable the boot partition 1 boot enabled.
"echo 8 > /sys/devices/soc0/soc.1/2100000.aips-bus/ 219c000.usdhc/mmc_host/mmc2/mmc2\:0001/boot_config"
In order to make sure that the re-read the ext-csd of card
can be completed successfully, add the method to wait for
the finish of the busy state.
- setup boot_info message output
Output bit means of important esd_csd register
Read esd_csd info each time when cat boot_info
becasue user may change config affect esd_csd
value.
- Boot partition access howto:
About the details, please refer to the guidance of
Documentation/mmc/mmc-dev-parts.txt
To enable write access to /dev/mmcblkXbootY, disable the forced
read-only access with:
echo 0 > /sys/block/mmcblkXbootY/force_ro
To re-enable read-only access:
echo 1 > /sys/block/mmcblkXbootY/force_ro
NOTE:
- The definitions of the EXT_CSD_PART_CONFIG and EXT_CSD_BOOT_BUS_WIDTH
+------------------------------------------------------------+
| Bit7 | Bit6 | Bit5 Bit4 Bit3 | Bit2 Bit1 Bit0 |
|------|----------|-----------------------|------------------|
| X | BOOT_ACK | BOOT_PARTITION_ENABLE | PARTITION_ACCESS |
+------------------------------------------------------------+
Bit7: Reserved
Bit6: always set to vaule '1' when boot_part is enabled
Bit[5:3]:
0x0 : Device not boot enabled (default)
0x1 : Boot partition 1 enabled for boot
0x2 : Boot partition 2 enabled for boot
0x7 : User area enabled for boot
Bit[2:0]:
0x0 : No access to boot partition (default)
0x1 : R/W boot partition 1
0x2 : R/W boot partition 2
+--------------------------------------------------------------------+
| Bit7 Bit6 Bit5 | Bit4 Bit3 | Bit2 | Bit1 Bit0 |
|----------------|----------------------------------|----------------|
| X | BOOT_MODE | RESET_BOOT_BUS_WIDTH | BOOT_BUS_WIDTH |
+--------------------------------------------------------------------+
Bit [4:3] : BOOT_MODE (non-volatile)
0x0 : Use single data rate + backward compatible timings in boot
operation (default)
0x1 : Use single data rate + high speed timings in boot operation mode
0x2 : Use dual data rate in boot operation
0x3 : Reserved
Bit [2]: RESET_BOOT_BUS_WIDTH (non-volatile)
0x0 : Reset bus width to x1, single data rate and backward compatible
timings after boot operation (default)
0x1 : Retain boot bus width and boot mode after boot operation
Bit[1:0] : BOOT_BUS_WIDTH (non-volatile)
0x0 : x1 (sdr) or x4 (ddr) bus width in boot operation mode (default)
0x1 : x4 (sdr/ddr) bus width in boot operation mode
0x2 : x8 (sdr/ddr) bus width in boot operation mode
0x3 : Reserved
- example of the boot_info:
boot_info:0x07;
ALT_BOOT_MODE:1 - Supports alternate boot method
DDR_BOOT_MODE:1 - Supports alternate dual data rate during boot
HS_BOOTMODE:1 - Supports high speed timing during boot
boot_size:2048KB
boot_partition:0x48;
BOOT_ACK:1 - Boot acknowledge sent during boot operation
BOOT_PARTITION-ENABLE: 1 - Boot partition 1 enabled
PARTITION_ACCESS:0 - No access to boot partition
boot_bus:0x00
BOOT_MODE:0 - Use single data rate + backward compatible timings
in boot operation
RESET_BOOT_BUS_WIDTH:0 - Reset bus width to x1, single data rate
and backwardcompatible timings after boot operation
BOOT_BUS_WIDTH:0 - x1 (sdr) or x4 (ddr) bus width in boot
operation mode
Xianzhong [Tue, 13 Aug 2013 15:16:24 +0000 (23:16 +0800)]
ENGR00274782 fixed gpu crash when baseAddress is not 0 or 2G
The baseAddress of contiguousVidMem is the actual physical address
which is not subtracted by gpu baseAddress, but the allocated physical address
has been subtracted by gpu baseAddress in gckVIDMEM_Lock,
so the invalid offset is produced and used to calculate the logical address.
Luwei Zhou [Tue, 22 Oct 2013 08:20:31 +0000 (16:20 +0800)]
ENGR00284648 mxc: mlb: clean up the MLB driver code.
This patch clean up the MLB driver code of i.MX6Q/DL AUTO.
* Reorder the head file alphabetically
* Fix code comments format
* Fix the lines over 80 characters
* Fix the return type to void for some private functions
Nicolin Chen [Thu, 17 Oct 2013 10:24:29 +0000 (18:24 +0800)]
ENGR00283079-1 ASoC: fsl: Implement different DMA buffer sizes
Each CPU DAI driver has its own defined DMA buffer size, so this patch just
drops the original one that uses a fixed size for all drivers and implements
a different DMA buffer size to each driver.
Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
Nicolin Chen [Wed, 23 Oct 2013 03:47:43 +0000 (11:47 +0800)]
ALSA: Add SoC on-chip internal ram support for DMA buffer allocation
Now it's quite common that an SoC contains its on-chip internal RAM.
By using this RAM space for DMA buffer during audio playback/record,
we can shutdown the voltage for external RAM to save power.
So add new DEV type with iram malloc()/free() and accordingly modify
current default mmap() for the iram circumstance.
attribute groups are much more flexible than just a list of attributes,
due to their support for visibility of the attributes, and binary
attributes. Add dev_groups to struct bus_type which should be used
instead of dev_attrs.
dev_attrs will be removed from the structure soon.
To make it easier for driver subsystems to work with attribute groups,
create the ATTRIBUTE_GROUPS macro to remove some of the repetitive
typing for the most common use for attribute groups.
Huang Shijie [Wed, 23 Oct 2013 08:05:42 +0000 (16:05 +0800)]
spi: spi-imx: only enable the clocks when we start to transfer a message
Current code keeps the clocks enabled all the time, it wastes the power
when there is no operaiton on the spi controller.
In order to save the power, this patch adds the two hooks:
spi_imx_prepare_message: enable the clocks for this message
spi_imx_unprepare_message: disable the clocks.
This patch also disables the clocks in the end of the probe.
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Jingoo Han [Mon, 14 Oct 2013 01:31:51 +0000 (10:31 +0900)]
spi: Fix checkpatch issue
Fix the following checkpatch error and warnings.
ERROR: space required after that ',' (ctx:VxV)
WARNING: quoted string split across lines
WARNING: max() should probably be max_t(int, nb, master->num_chipselect)
WARNING: sizeof *spi should be sizeof(*spi)
WARNING: sizeof *master should be sizeof(*master)
WARNING: sizeof x should be sizeof(x)
Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Sat, 5 Oct 2013 10:50:40 +0000 (11:50 +0100)]
spi: Provide common spi_message processing loop
The loops which SPI controller drivers use to process the list of transfers
in a spi_message are typically very similar and have some error prone areas
such as the handling of /CS. Help simplify drivers by factoring this code
out into the core - if drivers provide a transfer_one() function instead
of a transfer_one_message() function the core will handle processing at the
message level.
/CS can be controlled by either setting cs_gpio or providing a set_cs
function. If this is not possible for hardware reasons then both can be
omitted and the driver should continue to implement manual /CS handling.
This is a first step in refactoring and it is expected that there will be
further enhancements, for example factoring out of the mapping of transfers
for DMA and the initiation and completion of interrupt driven transfers.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Fri, 4 Oct 2013 23:23:12 +0000 (00:23 +0100)]
spi: Provide per-message prepare and unprepare operations
Many SPI drivers perform setup and tear down on every message, usually
doing things like DMA mapping the message. Provide hooks for them to use
to provide such operations.
This is of limited value for drivers that implement transfer_one_message()
but will be of much greater utility with future factoring out of standard
implementations of that function.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mika Westerberg [Thu, 10 Oct 2013 10:28:48 +0000 (13:28 +0300)]
spi: attach/detach SPI device to the ACPI power domain
If the SPI device is enumerated from ACPI namespace (it has an ACPI handle)
it might have ACPI methods that needs to be called in order to transition
the device to different power states (such as _PSx).
We follow what has been done for platform and I2C buses here and attach the
SPI device to the ACPI power domain if the device has an ACPI handle. This
makes sure that the device is powered on when its ->probe() is called.
For non-ACPI devices this patch is a no-op.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mark Brown <broonie@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Jarkko Nikula [Thu, 10 Oct 2013 14:19:17 +0000 (17:19 +0300)]
spi: Fix modalias for ACPI enumerated SPI devices
There is a minor fault about ACPI enumerated SPI devices with their modalias
attribute. Now modalias is set by device instance not by hardware ID.
For example "spi:INTABCD:00", "spi:INTABCD:01" etc.
This means each device instance gets different modalias which does match
with generated modules.alias. Currently this is not problem as matching can
happen also with "acpi:INTABCD" modalias.
Fix this by using ACPI hardware ID.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Mon, 7 Oct 2013 18:33:53 +0000 (19:33 +0100)]
spi: Provide trace points for message processing
Provide tracepoints for the lifecycle of a message from submission to
completion and for the active time for masters to help with performance
analysis of SPI I/O.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Instead of getting the raw property, checking the length, and doing
endian conversion each time, use the OF function
of_property_read_u32() that does all that.
Error messages are slightly improved with error codes from
of_property_read_u32() for different ways the property may be invalid
(missing, too short, etc.)
Signed-off-by: Trent Piepho <tpiepho@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Sat, 31 Aug 2013 17:50:52 +0000 (18:50 +0100)]
spi: core: Add devm_spi_register_master()
Help simplify the cleanup code for SPI master drivers by providing a
managed master registration function, ensuring that the master is
automatically unregistered whenever the device is unbound.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
The previous property name spi-tx-nbits and spi-rx-nbits looks not
human-readable. To make it consistent with other devices, using property
name spi-tx-bus-width and spi-rx-bus-width instead of the previous one
specify the number of data wires that spi controller will work in.
Add the specification in spi-bus.txt.
Signed-off-by: wangyuhang <wangyuhang2014@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Axel Lin [Sat, 31 Aug 2013 12:25:52 +0000 (20:25 +0800)]
spi: core: Fix spi_register_master error handling
In the case spi_master_initialize_queue() fails, current code calls
device_unregister() before return error from spi_register_master().
However, all the drivers call spi_master_put() in the error path if
spi_register_master() fails. Thus we should call device_del() rather than
device_unregister() before return error from spi_register_master().
This also makes all the spi_register_master() error handling consistent,
because all other error paths of spi_register_master() expect drivers to
call spi_master_put() if spi_register_master() fails.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Fri, 30 Aug 2013 22:19:40 +0000 (23:19 +0100)]
spi: quad: Make DT properties optional
The addition SPI quad support made the DT properties mandatory, breaking
compatibility with existing systems. Fix that by making them optional,
also improving the error messages while we're at it.
Signed-off-by: Mark Brown <broonie@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Axel Lin [Thu, 22 Aug 2013 15:41:34 +0000 (23:41 +0800)]
spi: Remove a redundant test for master->running in spi_queued_transfer
We have tested master->running immediately after grab the master->queue_lock.
The status of master->running won't be changed until we release the lock.
Thus remove a redundant test for master->running.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Sourav Poddar [Thu, 22 Aug 2013 15:50:48 +0000 (21:20 +0530)]
spi: conditional checking of mode and transfer bits.
There is a bug in the following patch:
http://comments.gmane.org/gmane.linux.kernel.spi.devel/14420
spi: DUAL and QUAD support
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = <1/2/4>" in place of using
"spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
(1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
single, dual and quad.
(2)keep tx_nbits and rx_nbits are contained by @spi_device->mode
example: if @spi_device->mode = DUAL, then tx/rx_nbits can not be set
to QUAD(SPI_NBITS_QUAD)
(3)if "@spi_device->mode & SPI_3WIRE", then tx/rx_nbits should be in
single(SPI_NBITS_SINGLE)
Checking of the tx/rx transfer bits and mode bits should be done conditionally
based on type of buffer filled else EINVAL condition will
always get hit either for rx or tx.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
wangyuhang [Sun, 11 Aug 2013 10:15:17 +0000 (18:15 +0800)]
spi: DUAL and QUAD support
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = <1/2/4>" in place of using
"spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
(1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
single, dual and quad.
(2)keep tx_nbits and rx_nbits are contained by @spi_device->mode
example: if @spi_device->mode = DUAL, then tx/rx_nbits can not be set
to QUAD(SPI_NBITS_QUAD)
(3)if "@spi_device->mode & SPI_3WIRE", then tx/rx_nbits should be in
single(SPI_NBITS_SINGLE)
Signed-off-by: wangyuhang <wangyuhang2014@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Gabor Juhos [Wed, 14 Aug 2013 08:25:28 +0000 (10:25 +0200)]
spi: limit default transfer speed to controller's max speed
Since the 'spi: Support transfer speed checking in the core'
change, the SPI core validates the desired speed of a given
transfer against the minimum and maximum speeds supported by
the controller.
If the speed of a transfer is not specified, the core uses
the maximum speed of the actual SPI device. However if the
maximum speed of the actual device is greater than the
maximum speed of the controller, the core will reject the
transfer due to the aforementioned change.
Change the code to use the maximum speed of the controller
by default if that is below the device's maximum speed.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Stephen Warren [Thu, 1 Aug 2013 22:08:57 +0000 (16:08 -0600)]
spi: fix SPI_BIT_MASK so it always fits into 32-bits
On a 64-bit platform, ~0UL fills 64-bits, which causes SPI_BIT_MASK(32)
not to fit into 32 bits. This causes a warning when the result is assigned
to a 32-bit variable. Use ~0U instead to prevent this. This fixes:
drivers/spi/spi-gpio.c: In function 'spi_gpio_probe':
drivers/spi/spi-gpio.c:446:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]
Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Sun, 28 Jul 2013 13:47:02 +0000 (14:47 +0100)]
spi: Provide core support for runtime PM during transfers
Most SPI drivers that implement runtime PM support use identical code to
do so: they acquire a runtime PM lock in prepare_transfer_hardware() and
then they release it in unprepare_transfer_hardware(). The variations in
this are mostly missing error checking and the choice to use autosuspend.
Since these runtime PM calls are normally the only thing in the prepare
and unprepare callbacks and the autosuspend API transparently does the
right thing on devices with autosuspend disabled factor all of this out
into the core with a flag to enable the behaviour.
Signed-off-by: Mark Brown <broonie@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Stephen Warren [Thu, 30 May 2013 15:59:40 +0000 (09:59 -0600)]
spi: fix incorrect handling of min param in SPI_BPW_RANGE_MASK
SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one
representing support for all bits up-to-and-including the "max" supported
value, and one representing support for all bits up-to-but-not-including
the "min" supported value, and then taking the difference between the
two, resulting in a mask representing support for all bits between
(inclusive) the min and max values.
However, the second mask ended up representing all bits up-to-and-
including rather up-to-but-not-including. Fix this bug.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Stephen Warren [Thu, 30 May 2013 15:59:39 +0000 (09:59 -0600)]
spi: fix undefined behaviour in SPI_BPW_RANGE_MASK
The parameters to SPI_BPW_RANGE_MASK() are in the range 1..32. If 32 is
used as a parameter, part of the expression is "1 << 32". Since 32 is >=
the size of the type in use, such a shift is undefined behaviour. Add
macro SPI_BIT_MASK to Implement a special case and thus avoid undefined
behaviour. Use this new macro rather than BIT() when implementing
SPI_BPW_RANGE_MASK().
This fixes build warnings such as:
drivers/spi/spi-gpio.c:446:2: warning: left shift count >= width of type [enabled by default]
SPI_BPW_MASK() already avoids this, since its parameter is also in range
1..32, yet it only shifts by up to one less than the input parameter.
Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Stephen Warren [Wed, 22 May 2013 02:36:34 +0000 (20:36 -0600)]
spi: introduce macros to set bits_per_word_mask
Introduce two macros to make setting up spi_master.bits_per_word_mask
easier, and avoid mistakes like writing BIT(n) instead of BIT(n - 1).
SPI_BPW_MASK is for a single supported value of bits_per_word_mask.
SPI_BPW_RANGE_MASK represents a contiguous set of bit lengths.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Jingoo Han [Mon, 14 Oct 2013 01:33:38 +0000 (10:33 +0900)]
spi: bitbang: Fix checkpatch issue
Fix the following checkpatch warnings
WARNING: sizeof *cs should be sizeof(*cs)
WARNING: please, no space before tabs
WARNING: space prohibited between function name and open parenthesis '('
WARNING: line over 80 characters
Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Axel Lin [Tue, 10 Sep 2013 07:43:41 +0000 (15:43 +0800)]
spi: bitbang: Let spi_bitbang_start() take a reference to master
Many drivers that use bitbang library have a leak on probe error paths.
This is because once a spi_master_get() call succeeds, we need an additional
spi_master_put() call to free the memory.
Fix this issue by moving the code taking a reference to master to
spi_bitbang_start(), so spi_bitbang_start() will take a reference to master on
success. With this change, the caller is responsible for calling
spi_bitbang_stop() to decrement the reference and spi_master_put() as
counterpart of spi_alloc_master() to prevent a memory leak.
So now we have below patten for drivers using bitbang library:
Signed-off-by: Axel Lin <axel.lin@ingics.com> Suggested-by: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> Acked-by: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
spi/bitbang: don't error out if there is no setup callback provided
It's perfectly valid not to have a setup callback when the probe routine
does all the needed things. So don't even check for this case and trust
the caller.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
spi: spi-bitbang: Fix conversion of spi_bitbang_transfer_one()
Since commit 2025172e3 (spi/bitbang: Use core message pump), the following
kernel crash is seen:
Unable to handle kernel NULL pointer dereference at virtual address 0000000d
pgd = 80004000
[0000000d] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 1 PID: 48 Comm: spi32766 Not tainted 3.11.0-rc1+ #4
task: bfa3e580 ti: bfb90000 task.ti: bfb90000
PC is at spi_bitbang_transfer_one+0x50/0x248
LR is at spi_bitbang_transfer_one+0x20/0x248
...
,and also the following build warning:
drivers/spi/spi-bitbang.c: In function 'spi_bitbang_start':
drivers/spi/spi-bitbang.c:436:31: warning: assignment from incompatible pointer type [enabled by default]
In order to fix it, we need to change the first parameter of
spi_bitbang_transfer_one() to 'struct spi_master *master'.
Tested on a mx6qsabrelite by succesfully probing a SPI NOR flash.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Fri, 5 Jul 2013 19:07:27 +0000 (20:07 +0100)]
spi/bitbang: Use core message pump
Convert drivers using bitbang to use the core mesasge pump infrastructure,
saving some code and meaning that these drivers get to take advantage of
work done on improving the core implementation.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Fri, 5 Jul 2013 11:06:44 +0000 (12:06 +0100)]
spi/bitbang: Factor out message transfer from message pump loop
In order to make it easier to convert to transfer_one_message() lift the
code that does the actual message transfer out of the work function that
implements the message pump. This should have no functional impact, it's
just a simple code motion patch.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Mark Brown [Fri, 5 Jul 2013 10:44:49 +0000 (11:44 +0100)]
spi/bitbang: Unexport spi_bitbang_transfer()
Currently no drivers use the ability to override spi_bitbang_transfer()
and if any started this would make it harder to convert the bitbang code
to use transfer_one_message() so remove the export in order to prevent
anyone starting.
Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
Sachin Kamat [Thu, 30 May 2013 08:08:09 +0000 (13:38 +0530)]
spi: spi-imx: Fix compilation error
Fix compilation error due to a typo introduced by commit 24778be20f
("spi: convert drivers to use bits_per_word_mask"). Without this patch
we get the following build errors:
drivers/spi/spi-imx.c: In function ‘spi_imx_setupxfer’:
drivers/spi/spi-imx.c:703:2: warning: no return statement in function returning non-void [-Wreturn-type]
drivers/spi/spi-imx.c: At top level:
drivers/spi/spi-imx.c:705:9: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before ‘->’ token
drivers/spi/spi-imx.c:707:2: error: expected identifier or ‘(’ before ‘return’
drivers/spi/spi-imx.c:708:1: error: expected identifier or ‘(’ before ‘}’ token
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Stephen Warren [Wed, 22 May 2013 02:36:35 +0000 (20:36 -0600)]
spi: convert drivers to use bits_per_word_mask
Fill in the recently added spi_master.bits_per_word_mask field in as
many drivers as possible. Make related cleanups, such as removing any
redundant error-checking, or empty setup callbacks.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
Jingoo Han [Fri, 3 May 2013 07:27:12 +0000 (16:27 +0900)]
spi: remove unnecessary platform_set_drvdata()
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d0631001288a5974afc0b2a5f568bcdecb4d
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00284019: [iMX6SL] Add low power mode optimizations
Add optimizations so that the low power IDLE mode numbers match
between the 3.10.9 and 3.0.35 kernel.
Optimizations include:
1. Disable unused PLLs and PFDs in clock init
2. Some of the drivers call clk_prepare in probe and enable much
later. clk_pllv3_prepare locks the PLL disallowing some of the low
power optimizations. For iMX6SL ensure that clk_pllv3_prepare does
not lock the PLL.
3. Ensure that MMDC_CH0_LPM_HS is set when WAIT mode is entered.
Dong Aisheng [Mon, 21 Oct 2013 08:54:40 +0000 (16:54 +0800)]
mmc: sdhci-esdhc-imx: add delay line setting support
The DLL(Delay Line) is newly added to assist in sampling read data.
The DLL provides the ability to programmatically select a quantized
delay (in fractions of the clock period) regardless of on-chip variations
such as process, voltage and temperature (PVT).
This patch adds a user interface to set slave delay line via device tree.
It's usually used in high speed mode like mmc DDR mode when the signal
quality is not good caused by board design, e.g. the signal path is too
long. User can manually set delay line to find a suitable data sampling
window for card to work properly.
Dong Aisheng [Mon, 21 Oct 2013 07:27:40 +0000 (15:27 +0800)]
mmc: sdhci-esdhc-imx: add DDR mode support for mx6
When DDR mode is enabled, the initial pre_div should be 2.
And the pre_div value should be changed accordingly
from
...
02h) Base clock divided by 4
01h) Base clock divided by 2
00h) Base clock divided by 1
to
..
02h) Base clock divided by 8
01h) Base clock divided by 4
00h) Base clock divided by 2
Dong Aisheng [Fri, 18 Oct 2013 11:48:45 +0000 (19:48 +0800)]
mmc: sdhci: report error once the maximum tuning loops exhausted or timeout
The original code missed to report an error when the maximum tuning
loops exhausted or timeout, it will cause the upper layer to wrongly
think the tuning process is passed.
Dong Aisheng [Mon, 21 Oct 2013 07:25:45 +0000 (15:25 +0800)]
mmc: sdhci-esdhc-imx: add std tuning support for mx6sl
The mx6sl supports standard sdhci tuning, then esdhc_executing_tuning
is only needed for mx6q/dl. We introduce is_imx6_usdhc() and
is_imx6sl_usdhc() to handle the difference.
The standard tuning is enabled by setting ESDHC_TUNE_CTRL_STD_TUNING_EN bit
in new register ESDHC_TUNE_CTRL and operates with new tuning bits
defined in SDHCI_ACMD12_ERR register.
Note: mx6sl can also work on the old manually tuning mode as mx6q/dl if
not enable standard tuning mode.
Create a struct esdhc_soc_data with moving 'flags' field from
pltfm_imx_data into it, and pass the pointer of this SoC specific data
structure through of_device_id.data directly, so that the translation
from enum imx_esdhc_type to flags can be saved.
With the change, enum imx_esdhc_type can be eliminated, since we can
implement the is_imx*_esdhc() by checking the esdhc_soc_data pointer.
The unused is_imx35_esdhc() and is_imx51_esdhc() are also removed, and the
others are kept there as we will need to use them to handle some small
register differences later, where use of new flags might be a little
overkilled.
Shawn Guo [Thu, 17 Oct 2013 07:19:46 +0000 (15:19 +0800)]
mmc: sdhci-esdhc-imx: pdev->id_entry should be immutable
As a good practice, device driver should not modify pdev->id_entry but
keep it immutable. Let's assign of_device_id.data with imx_esdhc_type
constants directly, so that we do not have to manipulate pdev->id_entry
in .probe().
As the result, sdhci-esdhc-imx53 and sdhci-usdhc-imx6q can be removed
from platform_device_id table now, since they will only probe from
device tree.
Dong Aisheng [Mon, 21 Oct 2013 07:23:31 +0000 (15:23 +0800)]
mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_USDHC
Add flag ESDHC_FLAG_USDHC to tell that the ESDHC is actually an USDHC
block, and replace the is_imx6q_usdhc() occurrences with inline function
esdhc_is_usdhc() which checks the flag.
Shawn Guo [Thu, 17 Oct 2013 07:19:44 +0000 (15:19 +0800)]
mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_ENGCM07207
Just like the use of the flag ESDHC_FLAG_MULTIBLK_NO_INT, let's add
another flag ESDHC_FLAG_ENGCM07207 to enable the workaround for errata
ENGcm07207 and set the flag for i.MX25 and i.MX35 ESDHC.
While at it, let's use BIT() macro for ESDHC_FLAG_MULTIBLK_NO_INT as
well.
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