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11 years agoENGR00161119 Codec regulator registration update
Mahesh Mahadevan [Mon, 31 Oct 2011 13:36:05 +0000 (08:36 -0500)]
ENGR00161119 Codec regulator registration update

Move the codec regulator registration code to the board
specific file

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00157253-2 MX6Q spi: update spi driver for MX6Q
Robin Gong [Fri, 28 Oct 2011 10:31:40 +0000 (18:31 +0800)]
ENGR00157253-2 MX6Q spi: update spi driver for MX6Q

update spi driver for MX6Q
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00157253-1 MX6Q spi: add ecspi for MX6Q
Robin Gong [Mon, 31 Oct 2011 01:55:25 +0000 (09:55 +0800)]
ENGR00157253-1 MX6Q spi: add ecspi for MX6Q

1.modify config
2.add board level support ecspi
3.add ecspi pad configure
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00160701 Fix the Micrel PHY driver
Mahesh Mahadevan [Mon, 24 Oct 2011 14:46:13 +0000 (09:46 -0500)]
ENGR00160701 Fix the Micrel PHY driver

Received a fix from Micrel to fix their driver. Without this
patch the Micrel PHY does not get recognized during boot

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00161005-2 MX6Q Kernel Rename sabreauto to arm2 board
Anish Trivedi [Fri, 28 Oct 2011 18:16:09 +0000 (13:16 -0500)]
ENGR00161005-2 MX6Q Kernel Rename sabreauto to arm2 board

Rename "sabreauto" config in sound driver to "arm2".

Signed-off-by: Anish Trivedi <anish@freescale.com>
11 years agoENGR00161005-1 MX6Q Kernel Rename sabreauto to arm2 board
Anish Trivedi [Fri, 28 Oct 2011 18:07:00 +0000 (13:07 -0500)]
ENGR00161005-1 MX6Q Kernel Rename sabreauto to arm2 board

Machine layer patch.

Sabreauto is an inaccurate name for the Armadillo2 board that
this code is actually meant for. So, renamed "sabreauto" board file,
configs, and code to "arm2". Created a new machine id for
ARM2 board.

Signed-off-by: Anish Trivedi <anish@freescale.com>
11 years agoENGR00160797-2 Add Anatop regulator driver
Nancy Chen [Thu, 27 Oct 2011 21:52:37 +0000 (16:52 -0500)]
ENGR00160797-2 Add Anatop regulator driver

Add Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
11 years agoENGR00160797-1 [i.MX6q] Add Anatop regulator support
Nancy Chen [Thu, 27 Oct 2011 21:49:24 +0000 (16:49 -0500)]
ENGR00160797-1 [i.MX6q] Add Anatop regulator support

1. Add Anatop regulator support.
2. Add some dummy regulators support for audio codec.

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
11 years agoENGR00160860-2 hdmi audio driver
Alan Tull [Tue, 25 Oct 2011 20:41:55 +0000 (15:41 -0500)]
ENGR00160860-2 hdmi audio driver

Audio driver for i.Mx built-in HDMI Transmitter.

* Uses HDMI Transmitter's built-in DMA.
* Adds IEC958-style digital audio header info to the raw audio.
* Gets pixel clock from the IPU driver and calculates clock
  regenerator values (cts and N).
* Move ipu_id, and disp_id from the HDMI's platform data to the
  HDMI mfd's platform data. Saves them in the hdmi mfd.
* Add mfd functionality to update the clock regenerator values
  when the hdmi changes the pixel clock rate or when requested
  from the audio driver with a new audio sample rate.

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00160860-1 hdmi audio driver
Alan Tull [Thu, 15 Sep 2011 20:51:33 +0000 (15:51 -0500)]
ENGR00160860-1 hdmi audio driver

Audio driver for i.Mx built-in HDMI Transmitter.

* Uses HDMI Transmitter's built-in DMA.
* Adds IEC958-style digital audio header info to the raw audio.
* Gets pixel clock from the IPU driver and calculates clock
  regenerator values (cts and N).
* Move ipu_id, and disp_id from the HDMI's platform data to the
  HDMI mfd's platform data. Saves them in the hdmi mfd.

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00160935 [MX6]Build out thermal driver
Anson Huang [Fri, 28 Oct 2011 02:03:50 +0000 (10:03 +0800)]
ENGR00160935 [MX6]Build out thermal driver

Build out thermal driver by default, since it will
cause system boot fail on the uncalibrated parts.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00160940-2 [MX6Q]sdhci: add delay line configuration
Tony Lin [Fri, 28 Oct 2011 05:52:45 +0000 (13:52 +0800)]
ENGR00160940-2 [MX6Q]sdhci: add delay line configuration

driver will configure the delay line setting due to board data
after DDR mode is enabled.

Signed-off-by: Tony Lin <tony.lin@freescale.com>
11 years agoENGR00160940-1 [MX6Q]sdhci: add delay line setting in board data
Tony Lin [Fri, 28 Oct 2011 05:50:59 +0000 (13:50 +0800)]
ENGR00160940-1 [MX6Q]sdhci: add delay line setting in board data

driver could set delay line due to board data parameter.

Signed-off-by: Tony Lin <tony.lin@freescale.com>
11 years agoENGR00160936 GPMI : disable the DDR code
Huang Shijie [Fri, 28 Oct 2011 02:33:07 +0000 (10:33 +0800)]
ENGR00160936 GPMI : disable the DDR code

We do not support any ONFI or TOGGLE nand now.
So disable the DDR code.

If keep it enabled, the ECC chunk will be 1K for ONFI nand,
this is not compatible with the kobs-ng which uses 512bytes for ECC chunk size.

So disable it now. change it in future.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00160798 [MX6]Workaround for NFS
Anson Huang [Wed, 26 Oct 2011 03:14:34 +0000 (11:14 +0800)]
ENGR00160798 [MX6]Workaround for NFS

Disable SCU standby mode will prevent SOC enter
WAIT mode, so, by default, we would not enable
WAIT mode to make NFS work, to enable WAIT mode,
you should not use NFS, and pass "enable_wait_mode"
from uboot.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz.
Ranjani Vaidyanathan [Wed, 19 Oct 2011 19:38:19 +0000 (14:38 -0500)]
ENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz.

When CPU frequency is below 400MHz (due to CPUFREQ or dvfs-core), we can source
pll1_sw_clk from PLL2_PFD_400M and disable PLL1. This can save some power.

Fixed warnings in dvfs_core driver.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00160863 Update clocking code to support all UARTs
Mahesh Mahadevan [Wed, 26 Oct 2011 15:36:39 +0000 (10:36 -0500)]
ENGR00160863 Update clocking code to support all UARTs

The MX6 Sabre-lite board uses UART2 for console. Add clock
code for this in the MX6 BSP

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160874 Enable SSI audio support on the MX6
Mahesh Mahadevan [Wed, 26 Oct 2011 21:52:48 +0000 (16:52 -0500)]
ENGR00160874 Enable SSI audio support on the MX6

The MX6 Sabre-lite board uses the SGTL codec through
SSI to play audio. Add support for SSI audio on the MX6

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160802-2 vpu: Check interrupt reason before disable clock
Sammy He [Wed, 26 Oct 2011 12:46:39 +0000 (20:46 +0800)]
ENGR00160802-2 vpu: Check interrupt reason before disable clock

There may be more interrupt than PIC_DONE reported, we cannot disable
clock if picture isn't done since vpu is still in busy in the status.
This patch will check interrupt reason before clock is disabled.

Signed-off-by: Sammy He <r62914@freescale.com>
11 years agoENGR00160802-1 arch/arm: Add BIT_INT_REASON reg definition in mxc_vpu.h
Sammy He [Wed, 26 Oct 2011 12:46:12 +0000 (20:46 +0800)]
ENGR00160802-1 arch/arm: Add BIT_INT_REASON reg definition in mxc_vpu.h

The BIT_INT_REASON register is needed in vpu driver code, so add it here.

Signed-off-by: Sammy He <r62914@freescale.com>
11 years agoENGR00160855 balance spinlock and irq enable in mxc hdmi video isr
Alan Tull [Wed, 26 Oct 2011 15:40:17 +0000 (10:40 -0500)]
ENGR00160855 balance spinlock and irq enable in mxc hdmi video isr

Need to add a spinlock unlock and irq enable at a return path.

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00160862 unique id for each soc-audio device
Alan Tull [Wed, 26 Oct 2011 18:13:47 +0000 (13:13 -0500)]
ENGR00160862 unique id for each soc-audio device

On boards which have more than one soc-audio device, the initialization
of the first device will create a sysfs directory named
/sys/devices/platform/soc-audio and subsequent soc-audio devices will
fail to init because they try to create another sysfs directory of the
same name.

The solution is to have a unique number for each device such that
different boards having combinations will be OK.

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00160847 Update AUDMUX driver for MX6Q
Mahesh Mahadevan [Tue, 25 Oct 2011 15:20:14 +0000 (10:20 -0500)]
ENGR00160847 Update AUDMUX driver for MX6Q

Add protection to ensure code runs on MX6Q only

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160834 UTP : replace kzalloc() with vmalloc()
Huang Shijie [Wed, 26 Oct 2011 09:31:25 +0000 (17:31 +0800)]
ENGR00160834 UTP : replace kzalloc() with vmalloc()

When allocating large memory, such as 128K,
vmalloc() uses single page for the allocation process,
while kzalloc() has to consume a continuous pages for the allocation.

In low memory case, the kzalloc() may fails.
So use the vmalloc() instead.

Also add some sanity check for the NULL pointer.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00159530-5 mc34708:modify config for new driver
Robin Gong [Mon, 10 Oct 2011 11:06:13 +0000 (19:06 +0800)]
ENGR00159530-5 mc34708:modify config for new driver

Modify imx5_defconfig for new mc34708's core driver,new regulator driver
and new rtc driver
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00159530-4 mc34708:add new mc34708's rtc driver
Robin Gong [Mon, 10 Oct 2011 10:51:17 +0000 (18:51 +0800)]
ENGR00159530-4 mc34708:add new mc34708's rtc driver

Add new mc34708's rtc driver based on new pmic core driver
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00159530-3 mc34708:add new regulator driver
Robin Gong [Mon, 10 Oct 2011 10:33:38 +0000 (18:33 +0800)]
ENGR00159530-3 mc34708:add new regulator driver

1.add new regulator driver for new pmic core driver
2.add Kconfig and Makefile

Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00159530-2 mc34708:add board level support for new pmic driver
Robin Gong [Mon, 10 Oct 2011 10:13:07 +0000 (18:13 +0800)]
ENGR00159530-2 mc34708:add board level support for new pmic driver

1.add new board level file related to new pmic driver
2.support for new board id for RevB of LOCO,so it can support
  both RevA and RevB boards

Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00159530-1 mc34708: add new pmic core driver based on MFD
Robin Gong [Mon, 10 Oct 2011 08:34:21 +0000 (16:34 +0800)]
ENGR00159530-1 mc34708: add new pmic core driver based on MFD

add new mc34708's core driver based on MFD
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00160512 SDMA: close clock when not used
Gary Zhang [Fri, 21 Oct 2011 03:28:23 +0000 (11:28 +0800)]
ENGR00160512 SDMA: close clock when not used

When SDMA is not used, close SDMA clock.

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00160692 - MXC HDMI: Unbalanced clk disable
Danny Nold [Mon, 24 Oct 2011 16:11:17 +0000 (11:11 -0500)]
ENGR00160692 - MXC HDMI: Unbalanced clk disable

HDMI IAHB clock was capable of being disabled twice consecutively
due to a race condition between enabling the HDMI interrupts
and disabling the HDMI clock.  A spinlock has been added to protect
against the race condition.

Another race condition was present due to the driver handling
HPD (hotplug detect) and RX Sense interrupts separately.  Only HPD
interrupts handled now, simplifying enable/disable flow and
eliminating the race condition.

One final race condition fixed during HDMI driver initialization.
IRQ request moved to after place where IAHB is disabled, to ensure
balanced enable/disable of IAHB clock.

Signed-off-by: Danny Nold <dannynold@freescale.com>
11 years agoENGR00160794 Update AUDMUX driver for MX6Q
Mahesh Mahadevan [Tue, 25 Oct 2011 14:23:46 +0000 (09:23 -0500)]
ENGR00160794 Update AUDMUX driver for MX6Q

Update the AUDMUX driver for MX6Q support

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160709-3 Move board specific code out of FEC driver
Mahesh Mahadevan [Tue, 25 Oct 2011 13:29:34 +0000 (08:29 -0500)]
ENGR00160709-3 Move board specific code out of FEC driver

Move the board specific code out of the FEC driver to the platform
layer

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160709-2 Move board specific code out of FEC driver
Mahesh Mahadevan [Tue, 25 Oct 2011 13:29:15 +0000 (08:29 -0500)]
ENGR00160709-2 Move board specific code out of FEC driver

Move the board specific code out of the FEC driver to the platform
layer

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160709-1 Move board specific code out of FEC driver
Mahesh Mahadevan [Tue, 25 Oct 2011 13:28:44 +0000 (08:28 -0500)]
ENGR00160709-1 Move board specific code out of FEC driver

Move the board specific code out of the FEC driver to the platform
layer

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160615 Clock updates to enable support clko
Mahesh Mahadevan [Fri, 21 Oct 2011 15:50:25 +0000 (10:50 -0500)]
ENGR00160615 Clock updates to enable support clko

Enable support for clko clock used for the audio codec
on MX6 Sabre-lite board

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00139265-4 mxc alsa soc spdif driver
Alan Tull [Tue, 28 Jun 2011 16:18:05 +0000 (11:18 -0500)]
ENGR00139265-4 mxc alsa soc spdif driver

* Add support for S/PDIF on i.Mx6

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00139265-3 mxc alsa soc spdif driver
Alan Tull [Tue, 28 Jun 2011 16:18:05 +0000 (11:18 -0500)]
ENGR00139265-3 mxc alsa soc spdif driver

* Add spdif block clock divider settings and spdif_clk_set_rate
  function to mxc_spdif_platform_data.

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00139265-2 mxc alsa soc spdif driver
Alan Tull [Tue, 28 Jun 2011 16:18:05 +0000 (11:18 -0500)]
ENGR00139265-2 mxc alsa soc spdif driver

* Add spdif block clock divider settings and spdif_clk_set_rate
  function to mxc_spdif_platform_data.

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00139265-1 spdif capture gets clock from spdif stream
Alan Tull [Thu, 20 Oct 2011 15:51:55 +0000 (10:51 -0500)]
ENGR00139265-1 spdif capture gets clock from spdif stream

The S/PDIF block's DPLL recovers the clock from the input
bitstream.  So S/PDIF capture rate is not dependent on
transmit clocks available.

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00160611 Update ALSA driver to initialize sooner
Mahesh Mahadevan [Fri, 21 Oct 2011 13:44:37 +0000 (08:44 -0500)]
ENGR00160611 Update ALSA driver to initialize sooner

All ALSA sound-cards are not registered, hence change the init to regular
module_init.

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00156766 [MX6Q]USB: Enable USB host1 function
make shi [Tue, 25 Oct 2011 08:23:51 +0000 (16:23 +0800)]
ENGR00156766 [MX6Q]USB: Enable USB host1 function

Add necessary implement to Enable USB host1 function

Signed-off-by: make shi <b15407@freescale.com>
11 years agoENGR00160667 mx53 ard: fix ethernet unwork
Dong Aisheng [Mon, 24 Oct 2011 13:26:59 +0000 (21:26 +0800)]
ENGR00160667 mx53 ard: fix ethernet unwork

1) use smsc911x instead of smc911x
The smsc911x is supposed to replace the old smc911x driver.
2) fix the wrong chip select address

Signed-off-by: Dong Aisheng <b29396@freescale.com>
11 years agoENGR00160626 fix system hang when ipu clk get rate
Yuxi [Mon, 24 Oct 2011 06:22:16 +0000 (14:22 +0800)]
ENGR00160626 fix system hang when ipu clk get rate

Enable ipu clk when try  get rate

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00160547 vpu: Add vpu_reset function in arch/arm for i.mx6q
Sammy He [Fri, 21 Oct 2011 16:45:25 +0000 (00:45 +0800)]
ENGR00160547 vpu: Add vpu_reset function in arch/arm for i.mx6q

Add vpu hardware reset function for i.mx6q platform.

Signed-off-by: Sammy He <r62914@freescale.com>
11 years agoENGR00160602 Fix MX6 IOMUX Pad configuration code
Mahesh Mahadevan [Fri, 21 Oct 2011 10:25:06 +0000 (05:25 -0500)]
ENGR00160602 Fix MX6 IOMUX Pad configuration code

Increase the number of bits for Pad configuration by one
[Jason]: Merged conflict, removing the dumplicated def for NO_PAD_CTRL

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160605 Update ALSA Headset detect code
Mahesh Mahadevan [Fri, 21 Oct 2011 11:17:52 +0000 (06:17 -0500)]
ENGR00160605 Update ALSA Headset detect code

Update Headset detect code incase no dedicated pin and detect is
always activated

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
11 years agoENGR00160513 [MX6Q]Lower SOC power in dormant
Anson Huang [Fri, 21 Oct 2011 02:48:56 +0000 (10:48 +0800)]
ENGR00160513 [MX6Q]Lower SOC power in dormant

Add necessary implement to lower the SOC power
when dormant, on ddr3, ARM+SOC is ~3.8mA, and
on LPDDR2, it is ~2.3mA.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00160296: MX6-Added secondary and dependent clocks for various peripherals.
Ranjani Vaidyanathan [Tue, 18 Oct 2011 18:59:07 +0000 (13:59 -0500)]
ENGR00160296: MX6-Added secondary and dependent clocks for various peripherals.

Add secondary and dependent clocks for efficient clock management
and thereby reduce power.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00160397: Fix build break caused by DVFS-CORE driver
Ranjani Vaidyanathan [Wed, 19 Oct 2011 22:38:37 +0000 (17:38 -0500)]
ENGR00160397: Fix build break caused by DVFS-CORE driver

loops_per_jiffy is a global variable for non-smp platforms.
For SMP platforms, loops_per_jiffy is a per_cpu variable.
Fix dvfs_core to adjust loops_per_jiffy for both configurations.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00160112-4 camera: Add sensor clock setting for MX6
Yuxi [Mon, 17 Oct 2011 05:50:30 +0000 (13:50 +0800)]
ENGR00160112-4 camera: Add sensor clock setting for MX6

When the platform is MX6, set mclk = cko1_clk0

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00160112-3 MX6Q camera: config MCLK for csi0
Yuxi [Mon, 17 Oct 2011 05:46:03 +0000 (13:46 +0800)]
ENGR00160112-3 MX6Q camera: config MCLK for csi0

set cko1_clk0 as mclk for csi0

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00160112-2 MX6Q camera: Add camera data and initial pin configuration
Yuxi [Mon, 17 Oct 2011 05:41:15 +0000 (13:41 +0800)]
ENGR00160112-2 MX6Q camera: Add camera data and initial pin configuration

Add camera platform data and i2c bus data and initialize control pins

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00160112-1 MX6: Set csi0 and camera control pin pad configuration
Yuxi [Mon, 17 Oct 2011 05:29:16 +0000 (13:29 +0800)]
ENGR00160112-1 MX6: Set csi0 and camera control pin pad configuration

Set csi0 and camera control pin pad configuration

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00160061 - MXC HDMI: Optimize HDMI clock management
Danny Nold [Fri, 14 Oct 2011 18:43:32 +0000 (13:43 -0500)]
ENGR00160061 - MXC HDMI: Optimize HDMI clock management

- Ensure HDMI clocks are disabled when leaving HDMI core probe function.
- Create HDMI core api to allow HDMI sub-drivers to init, enable, and
disable the HDMI IRQ.  Required to optimally manage HDMI clocks,
allow IAHB to be disabled, and still have video and audio sub-drivers
able to receive interrupts.
- Update code to adjust for decoupled ISFR and IAHB clocks.
- Disable IAHB clocks whenever HDMI not plugged in.

Signed-off-by: Danny Nold <dannynold@freescale.com>
11 years agoENGR00160061 - Mach-MX6: Optimize HDMI clock management
Danny Nold [Fri, 14 Oct 2011 17:50:39 +0000 (12:50 -0500)]
ENGR00160061 - Mach-MX6: Optimize HDMI clock management

- Decouple HDMI IAHB clock from HDMI ISFR clock, in order to
allow IAHB clock to be disabled while keeping ISFR clock enabled.

Signed-off-by: Danny Nold <dannynold@freescale.com>
11 years agoENGR00160291 MX6 correct cdcdr spdif0 podf defines
Alan Tull [Tue, 18 Oct 2011 18:09:28 +0000 (13:09 -0500)]
ENGR00160291 MX6 correct cdcdr spdif0 podf defines

MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET/MASK were incorrect.  Should be 22.

Signed-off-by: Alan Tull <alan.tull@freescale.com>
11 years agoENGR00160241 [mx6q]sdhci: kernel panic caused by clock enable in interrupt
Tony Lin [Tue, 18 Oct 2011 08:20:51 +0000 (16:20 +0800)]
ENGR00160241 [mx6q]sdhci: kernel panic caused by clock enable in interrupt

cancel the timer even in interrupt context to fix following error log:

clk_enable cannot be called in an interrupt context
kernel BUG at arch/arm/plat-mxc/clock.c:104!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = 80004000
[00000000] *pgd=00000000
Internal error: Oops: 805 [#1] PREEMPT SMP
last sysfs file: /sys/devices/platform/fsl-ehci.1/usb2/2-0:1.0/uevent
Modules linked in:
CPU: 1    Tainted: G        W    (2.6.38-00559-g4938069-dirty #30)
PC is at __bug+0x18/0x24
LR is at __bug+0x14/0x24
pc : [<80039eec>]    lr : [<80039ee8>]    psr: 20000193
sp : e6067eb8  ip : ec91a000  fp : 00000000
r10: 8002eacc  r9 : 805738e0  r8 : 00000023
r7 : 60000113  r6 : e67c92a8  r5 : 00000001  r4 : 8054d8f8
r3 : 00000000  r2 : 00000104  r1 : 60000193  r0 : 00000033
Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c53c7d  Table: 7461804a  DAC: 00000015
Process swapper (pid: 0, stack limit = 0xe60662f0)
Stack: (0xe6067eb8 to 0xe6068000)
7ea0:                                                       8054d8f8 8004914c
7ec0: e67c9280 802fa9e4 e67c9280 00000100 e67c92a8 802f7754 e67c9280 e61ade14
7ee0: e67c92a8 802f8f60 e67c9324 e67c9328 00000000 e6066000 80547c40 802ebe80
7f00: e67c9324 8005d828 8005d71c 00000018 00000001 e6066000 80538040 80538040
7f20: 805738e0 00000103 8002e9f4 8005dbf0 2faf2e40 0000030e 2faf2e40 00000006
7f40: 00000009 00000001 00000000 80547c40 8002f380 00000000 80573900 00000001
7f60: e6066000 00000000 00000000 8005dd30 80547c40 80030390 ffffffff f2a00100
7f80: 0000001d 00000002 00000001 8003600c 00000020 80547a84 e6067fd8 00000000
7fa0: e6066000 8056e1e4 803fdd54 8054ae9c 70000000 412fc09a 00000000 00000000
7fc0: 00000000 e6067fd8 800372ac 800372b0 60000013 ffffffff e6066000 800378d8
7fe0: 7606806a 00000015 10c03c7d 8056e36c 70000000 103f628c 78fffff6 debdbeb9
(__bug+0x18/0x24) from [<8004914c>] (clk_enable+0x100/0x118)
(clk_enable+0x100/0x118) from [<802fa9e4>] (plt_clk_ctrl+0x28/0x34)
(plt_clk_ctrl+0x28/0x34) from [<802f7754>] (sdhci_enable_clk+0x5c/0x80)
(sdhci_enable_clk+0x5c/0x80) from [<802f8f60>] (sdhci_request+0xac/0x188)
(sdhci_request+0xac/0x188) from [<802ebe80>] (mmc_request_done+0x74/0x78)
(mmc_request_done+0x74/0x78) from [<8005d828>] (tasklet_action+0x10c/0x15c)
(tasklet_action+0x10c/0x15c) from [<8005dbf0>] (__do_softirq+0xa8/0x140)
(__do_softirq+0xa8/0x140) from [<8005dd30>] (irq_exit+0xa8/0xb0)
(irq_exit+0xa8/0xb0) from [<80030390>] (do_local_timer+0x54/0x7c)
(do_local_timer+0x54/0x7c) from [<8003600c>] (__irq_svc+0x4c/0xe8)
Exception stack(0xe6067f90 to 0xe6067fd8)
7f80:                                     00000020 80547a84 e6067fd8 00000000
7fa0: e6066000 8056e1e4 803fdd54 8054ae9c 70000000 412fc09a 00000000 00000000
7fc0: 00000000 e6067fd8 800372ac 800372b0 60000013 ffffffff
......

Signed-off-by: Tony Lin <tony.lin@freescale.com>
11 years agoENGR00160085 MX6Q: add updater config file for MFGTOOL
Huang Shijie [Mon, 17 Oct 2011 03:31:43 +0000 (11:31 +0800)]
ENGR00160085 MX6Q: add updater config file for MFGTOOL

add the updater config file for mfgtool.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00139279 MX6Q: support the MFGTOOL
Huang Shijie [Wed, 14 Sep 2011 09:34:54 +0000 (17:34 +0800)]
ENGR00139279 MX6Q: support the MFGTOOL

fix ioctls.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00159641: MX6-Add DVFS-CORE support
Ranjani Vaidyanathan [Fri, 7 Oct 2011 17:35:29 +0000 (12:35 -0500)]
ENGR00159641: MX6-Add DVFS-CORE support

Add DVFS-CORE support for MX6 quad/dual SOC.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00159959: MX6-Updated CPU voltages for different frequencies
Ranjani Vaidyanathan [Thu, 13 Oct 2011 18:22:24 +0000 (13:22 -0500)]
ENGR00159959: MX6-Updated CPU voltages for different frequencies

Update CPU voltages for different frequencies based on characterized values.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00159796 [MX6]Cooling of cpufreq should consider governor type
Anson Huang [Tue, 11 Oct 2011 12:15:21 +0000 (20:15 +0800)]
ENGR00159796 [MX6]Cooling of cpufreq should consider governor type

We need to consider governor type of cpufreq, previous
method is to change the cpufreq to the lower point, but
it would not work if the cpufreq governor is not userspace,
now we set the scaling max freq instead of cpu current freq,
this will make sure working for all the governor.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00159737 [Mx6]Add clock check for periph clk
Anson Huang [Tue, 11 Oct 2011 12:03:16 +0000 (20:03 +0800)]
ENGR00159737 [Mx6]Add clock check for periph clk

For lpddr2 board, current freq only support up to
400MHz, in this case, periph clk will set to 400M
in uboot, so in clock init, we need to check
whether the ddr clock is set to 400M, if yes, then
we should set periph clk parent to pll2_pfd_400M.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00159738 v4l2: correct wrong parameter when V4l2 set window size
Yuxi Sun [Wed, 12 Oct 2011 04:17:02 +0000 (12:17 +0800)]
ENGR00159738 v4l2: correct wrong parameter when V4l2 set window size

Correct wrong parameter when call ipu_csi_set_window_size function

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00155879: MX6: Enable ARM core to enter WAIT mode when system is idle.
Ranjani Vaidyanathan [Thu, 1 Sep 2011 15:04:06 +0000 (10:04 -0500)]
ENGR00155879: MX6: Enable ARM core to enter WAIT mode when system is idle.

Set the appropriate bit in CCM to allow ARM-CORE to enter WAIT
mode when system is idle.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00156635 [MX6]Dormant random resume fail
Anson Huang [Sun, 9 Oct 2011 01:47:20 +0000 (09:47 +0800)]
ENGR00156635 [MX6]Dormant random resume fail

1. sometimes system can not resume successfully from
dormant mode, there is still some defect with L2 cache
array alive during dromant mode, add clean operation
before dormant to make sure data alignment between L2
and DRAM, after doing it, dormant mode can resume fine.

2. local time no need to do store and restore during
suspend/resume.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00156745 MX6Q ESAI: Playback and record can't start up concurrently
Lionel Xu [Fri, 30 Sep 2011 06:47:31 +0000 (14:47 +0800)]
ENGR00156745 MX6Q ESAI: Playback and record can't start up concurrently

Proper flag setting and placement should be used to avoid function hw_param
called multiple times when playback and record startup concurrently.

Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
11 years agoENGR00159512 [Mx6]Fix thermal driver build warning
Anson Huang [Sun, 9 Oct 2011 02:38:56 +0000 (10:38 +0800)]
ENGR00159512 [Mx6]Fix thermal driver build warning

1. Print should use %d instead of %ld when printing
   a unsigned int;
2. Remove unused function.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00159008-2 mx6 v4l2: build v4l2 relative modules as module mode
Yuxi Sun [Sat, 8 Oct 2011 04:46:17 +0000 (12:46 +0800)]
ENGR00159008-2 mx6 v4l2: build v4l2 relative modules as module mode

Change v4l2 relative modules as module mode when build kernel

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00159008-1 mx5 v4l2: build v4l2 relative modules as module mode
Yuxi Sun [Sat, 8 Oct 2011 04:43:41 +0000 (12:43 +0800)]
ENGR00159008-1 mx5 v4l2: build v4l2 relative modules as module mode

Change v4l2 relative modules as module mode when build kernel

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00159007 [MX6]Add cpufreq cooling device
Anson Huang [Fri, 30 Sep 2011 08:50:30 +0000 (16:50 +0800)]
ENGR00159007 [MX6]Add cpufreq cooling device

Add cpufreq as cooling device.

1.Default cooling device is cpufreq, to select
  cpuhotplug as cooling device, need to add
  cooling_device=cpuhotplug to cmdline.

2.Cooling device can be disabled via adding
  no_cooling_device to cmdline.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoSAUCE: set correct rates before registering SPDIF codec DAI
Eric Miao [Mon, 26 Sep 2011 02:46:27 +0000 (10:46 +0800)]
SAUCE: set correct rates before registering SPDIF codec DAI

BugLink: http://bugs.launchpad.net/bugs/855281
Playback/capture rates should be configured before the SPDIF codec
DAI is registered, according to the parameters that passed in by
the platform data. And this caused pulseaudio not working with the
SPDIF sound card.

Signed-off-by: Eric Miao <eric.miao@linaro.org>
11 years agoENGR00156637 [MX6]Reboot take long time on SMP
Anson Huang [Tue, 27 Sep 2011 10:20:19 +0000 (18:20 +0800)]
ENGR00156637 [MX6]Reboot take long time on SMP

Add work around to the reboot issue of SMP, with
SMP, all the CPUs need to do _rcu_barrier, if we
enqueue an rcu callback, we need to make sure CPU
tick to stay alive until we take care of those by
completing the appropriate grace period.

This work around only work when the reboot command
issue, so it didn't impact normal kernel feature.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00158456-2 ipuv3 dev: return error for split mode with rotation
Jason Chen [Thu, 29 Sep 2011 01:22:32 +0000 (09:22 +0800)]
ENGR00158456-2 ipuv3 dev: return error for split mode with rotation

Currently we do not support split mode with rotation.

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00158456-1 ipuv3 dev: return error for split mode with rotation
Jason Chen [Thu, 29 Sep 2011 01:22:07 +0000 (09:22 +0800)]
ENGR00158456-1 ipuv3 dev: return error for split mode with rotation

Currently we do not support split mode with rotation.

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00158152 v4l2 capture: changes based on ipu changes
Yuxi Sun [Mon, 26 Sep 2011 02:52:15 +0000 (10:52 +0800)]
ENGR00158152 v4l2 capture: changes based on ipu changes

v4l2 capture changes based on ipu change.

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00158176 SGTL5000: I/O Error appeared when recording mono wav through HW
Lionel Xu [Mon, 26 Sep 2011 08:46:00 +0000 (16:46 +0800)]
ENGR00158176 SGTL5000: I/O Error appeared when recording mono wav through HW

When recording mono wav, SSI's network mode should be closed, or it will
influence the internal freq config, making recording fail.

Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
11 years agoENGR00156976 - PxP: fix imx-lib build break
Danny Nold [Fri, 16 Sep 2011 16:53:34 +0000 (11:53 -0500)]
ENGR00156976 - PxP: fix imx-lib build break

Change from u8 declaration in pxp_dma.h to __u8

Signed-off-by: Danny Nold <dannynold@freescale.com>
11 years agoENGR00156420 - EPDC/PxP: Add support for color map
Danny Nold [Fri, 12 Aug 2011 01:07:59 +0000 (20:07 -0500)]
ENGR00156420 - EPDC/PxP: Add support for color map

- Add support for 8-bit grayscale colormaps to be used
during EPDC update processing
- Add support in PxP for programming of colormaps

Signed-off-by: Danny Nold <dannynold@freescale.com>
11 years agoENGR00157457 - MXC HDMI: Add support for non-CEA spec video modes
Danny Nold [Thu, 22 Sep 2011 21:43:24 +0000 (16:43 -0500)]
ENGR00157457 - MXC HDMI: Add support for non-CEA spec video modes

- Updated PHY configuration code to support ranges of clock frequencies,
rather than just a small set of supported clock frequencies corresponding
to CEA-861 video modes.  This means that PC monitor modes are now
supported.
- Updated color handling code to ensure that a consistent set of
color mode defines are used.
- Fixed bug in how clock disable registers are configured

Signed-off-by: Danny Nold <dannynold@freescale.com>
11 years agoENGR00157467: i.MX6/defconfig: enable ARM errata:754322
Jason Liu [Fri, 23 Sep 2011 02:51:53 +0000 (10:51 +0800)]
ENGR00157467: i.MX6/defconfig: enable ARM errata:754322

We need enable the following ARM errata software workaround:
754322: Possible faulty MMU translations following an ASID switch.

CONFIG_ARM_ERRATA_754322=y

These ERRATAs applied to i.MX6Q(cortex-a9:r2p10 smp)

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00157155-2 vpu: Get resource by platform_get_resource_byname
Sammy He [Tue, 20 Sep 2011 16:38:57 +0000 (00:38 +0800)]
ENGR00157155-2 vpu: Get resource by platform_get_resource_byname

Update code to be nicer, use platform_get_resource_byname() function to
get platform resource, and use platform_get_irq_byname() to get irq.

Signed-off-by: Sammy He <r62914@freescale.com>
11 years agoENGR00157155-1 vpu: Add vpu resource name in platform in arch/arm
Sammy He [Tue, 20 Sep 2011 16:35:02 +0000 (00:35 +0800)]
ENGR00157155-1 vpu: Add vpu resource name in platform in arch/arm

Add vpu resource name in platform in arch/arm, then vpu driver can
get resource by name.

Signed-off-by: Sammy He <r62914@freescale.com>
11 years agoENGR00156996 ipuv3: fix pixel clock look up table
Jason Chen [Mon, 19 Sep 2011 05:57:12 +0000 (13:57 +0800)]
ENGR00156996 ipuv3: fix pixel clock look up table

if there are two ipu, they will use same pixel look up table.
which will confuse get_clk

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00157032 i.MX6/defconfig: enable ARM errata software workaround
Jason Liu [Mon, 19 Sep 2011 08:32:54 +0000 (16:32 +0800)]
ENGR00157032 i.MX6/defconfig: enable ARM errata software workaround

We need enable the following ARM errata software workaround:

CONFIG_ARM_ERRATA_743622=y
CONFIG_ARM_ERRATA_751472=y

These ERRATAs applied to i.MX6Q(cortex-a9:r2p10 smp)

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00156850 gpu-viv: add gpu-viv driver source
Richard Zhao [Thu, 15 Sep 2011 08:42:04 +0000 (16:42 +0800)]
ENGR00156850 gpu-viv: add gpu-viv driver source

It's vivante driver 4.5.0 (Sep 5, 2011) with freescale changes.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00156813 MX53 ALSA: Recording no sound
Lionel Xu [Thu, 15 Sep 2011 07:44:26 +0000 (15:44 +0800)]
ENGR00156813 MX53 ALSA: Recording no sound

There is no sound in the recorded wav, to enable recording, the VAG should be
powered up, and the mic bias resistor should be setup with proper value.

Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
11 years agoARM: twd: register clockevents device before enabling PPI
Will Deacon [Wed, 20 Jul 2011 13:18:46 +0000 (14:18 +0100)]
ARM: twd: register clockevents device before enabling PPI

The smp_twd clockevents driver currently enables the local timer PPI
before the clockevents device is registered. This can lead to a kernel
panic if a spurious timer interrupt is generated before registration
has completed since the kernel will treat it as an IPI timer.

This patch moves the clockevents device registration before the IRQ
unmasking so that we can always handle timer interrupts once they can
occur.

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
11 years agoENGR00156849 MX6Q: add relative clock for BCH
Huang Shijie [Thu, 15 Sep 2011 11:22:12 +0000 (19:22 +0800)]
ENGR00156849 MX6Q: add relative clock for BCH

The BCH needs the pl301_mx6qperl_bch clock.
The BCH will not work if the clock is not enabled.
So add it.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00156319-2 mxc edid: use vmode as aspect rate flag
Jason Chen [Tue, 13 Sep 2011 05:01:50 +0000 (13:01 +0800)]
ENGR00156319-2 mxc edid: use vmode as aspect rate flag

Use vmode as aspect rate flag.
which is more easier to use.

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00156319-1 mxc edid: use vmode as aspect rate flag
Jason Chen [Fri, 9 Sep 2011 04:48:19 +0000 (12:48 +0800)]
ENGR00156319-1 mxc edid: use vmode as aspect rate flag

Use vmode as aspect rate flag.
which is more easier to use.

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00156673-3 ipuv3: move mach related definition to mach dir
Jason Chen [Wed, 14 Sep 2011 02:31:41 +0000 (10:31 +0800)]
ENGR00156673-3 ipuv3: move mach related definition to mach dir

for driver files.

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00156673-2 ipuv3: move mach related definition to mach dir
Jason Chen [Wed, 14 Sep 2011 02:26:24 +0000 (10:26 +0800)]
ENGR00156673-2 ipuv3: move mach related definition to mach dir

for arch/arm/plat-mxc/include/mach/ipu-v3.h

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00156673-1 ipuv3: move mach related definition to mach dir
Jason Chen [Wed, 14 Sep 2011 02:25:42 +0000 (10:25 +0800)]
ENGR00156673-1 ipuv3: move mach related definition to mach dir

for include/linux/ipu.h.

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00156374 ipuv3: check channel busy while wait disable irq
Jason Chen [Fri, 9 Sep 2011 09:53:24 +0000 (17:53 +0800)]
ENGR00156374 ipuv3: check channel busy while wait disable irq

there is chance channel already quit busy before wait disable
irq in ipu_disable_channel, so add check during irq wait.

this patch also comments f_calc and m_calc fix build warning.

Signed-off-by: Jason Chen <b02280@freescale.com>
11 years agoENGR00156314-3 [mx6q]gic: save/restore mode for suspend/resume
Tony Lin [Fri, 9 Sep 2011 03:45:11 +0000 (11:45 +0800)]
ENGR00156314-3 [mx6q]gic: save/restore mode for suspend/resume

save gic registers before suspend and restore these registers after resuming

Signed-off-by: Tony Lin <tony.lin@freescale.com>
11 years agoENGR00156314-2 [mx6q]gic: save/restore mode for suspend/resume
Tony Lin [Fri, 9 Sep 2011 03:45:11 +0000 (11:45 +0800)]
ENGR00156314-2 [mx6q]gic: save/restore mode for suspend/resume

add code to gic.c for common gic state save/restore.

Signed-off-by: Tony Lin <tony.lin@freescale.com>
11 years agoENGR00156314-1 [mx6q]gic: add comments to explain start irq offset value
Tony Lin [Fri, 9 Sep 2011 03:45:11 +0000 (11:45 +0800)]
ENGR00156314-1 [mx6q]gic: add comments to explain start irq offset value

to be more clear why we start irq offset from 29.
and list the irq ID table.

Signed-off-by: Tony Lin <tony.lin@freescale.com>
11 years agoENGR00156300 - EPDC fb: Move ISR code to work Q & replace spinlocks with mutexes
Danny Nold [Thu, 8 Sep 2011 20:38:25 +0000 (15:38 -0500)]
ENGR00156300 - EPDC fb: Move ISR code to work Q & replace spinlocks with mutexes

- Move the majority of code from the IRQ handler routine into a workqueue
routine.  This should improve system interrupt latency.
- Change the spin_lock protecting EPDC queues into a mutex and change all
associated spin_lock calls into mutex calls.

Signed-off-by: Danny Nold <dannynold@freescale.com>