* pm-tools:
cpupower: Remove mc and smt power aware scheduler info/settings
cpupower: cpupower info -b should return 0 on success, not the perf bias value
cpupower: If root, try to load msr driver on x86 if /dev/cpu/0/msr is not available
cpupower: Install recently added cpupower-idle-{set, info} manpages
cpupower: Introduce idle state disable-by-latency and enable-all
cpupower: Remove all manpages on make uninstall
cpupower: Remove dead link to homepage, and update the targets built.
cpupower: Rename cpufrequtils -> cpupower, and libcpufreq -> libcpupower.
* acpica-next:
ACPICA: Clean up redudant definitions already defined elsewhere
ACPICA: Linux headers: Add <asm/acenv.h> to remove mis-ordered inclusion of <asm/acpi.h>
ACPICA: Linux headers: Add <acpi/platform/aclinuxex.h>
ACPICA: Linux headers: Remove ACPI_PREEMPTION_POINT() due to no usages.
Mark Brown [Fri, 9 May 2014 18:18:08 +0000 (19:18 +0100)]
PM / OPP: Make OPP invisible to users in Kconfig
The OPP code is an in kernel library selected by its users, there is no
no architecture code required to implement it and enabling it without a
user just increases the kernel size. Since the users select rather than
depend on it just remove the ability to directly set the option from
Kconfig.
Signed-off-by: Mark Brown <broonie@linaro.org> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Chander Kashyap [Fri, 16 May 2014 10:51:17 +0000 (16:21 +0530)]
PM / OPP: fix incorrect OPP count handling in of_init_opp_table
In of_init_opp_table function, if a failure to add an OPP is
detected, the count of OPPs, yet to be added is not updated.
Fix this by decrementing this count on failure as well.
Antoine Tenart [Sun, 18 May 2014 18:15:57 +0000 (20:15 +0200)]
ARM: dts: berlin: add the pinctrl node and muxing setup for uarts
Add pinctrl bindings and system control nodes to what we currently know
about Berlin SoCs. Where available, also set default pinctrl property
for uarts, when there is only one pinmux option for it.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Antoine Tenart [Mon, 5 May 2014 05:27:28 +0000 (07:27 +0200)]
dt-binding: ARM: add pinctrl binding docs for Marvell Berlin2 SoCs
Add pin control binding documentation to the SoC binding documentaion
as pinctrl is part of chip/system control registers. The documentation
also explains how to configure this group based controller.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This converts Berlin BG2 SoC dtsi to make use of the new DT clock
nodes for Berlin SoCs. While at it, also fix up twdclk which is
running at cpuclk/3 instead of sysclk.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
dt-binding: ARM: add clock binding docs for Marvell Berlin2 SoCs
This adds mandatory device tree binding documentation for the clock related
IP found on Marvell Berlin2 (BG2, BG2CD, and BG2Q) SoCs to the Berlin SoC
binding documentation.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q
This adds scu and general purpose registers device nodes required for
SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
address from general purpose (SW generic) register 1.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Jisheng Zhang <jszhang@marvell.com> Tested-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Antoine Tenart [Tue, 18 Mar 2014 14:32:47 +0000 (15:32 +0100)]
ARM: dts: berlin: add the Marvell BG2-Q DMP device tree
Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Antoine Tenart [Tue, 18 Mar 2014 14:32:45 +0000 (15:32 +0100)]
ARM: dts: berlin: add the Marvell Armada 1500 pro
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now. Also add corresponding binding documentation.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Shawn Guo [Sat, 17 May 2014 12:46:01 +0000 (20:46 +0800)]
ahci: imx: PLL clock needs 100us to settle down
The commit e783c51 (ahci: imx: software workaround for phy reset issue
in resume) calls imx_sata_phy_reset() to reset phy immediately after
SATA MPLL is enabled. It seems working fine mostly, but fails in some
case as below.
...
ahci-imx 2200000.sata: failed to reset phy: -110
ahci-imx: probe of 2200000.sata failed with error -110
After talking to the designer, we learnt that when enabling i.MX6Q SATA
MPLL, we need to wait 100us for it to settle down for safety. Add this
required delay to fix above failure.
Gavin Shan [Mon, 19 May 2014 03:06:46 +0000 (13:06 +1000)]
PCI: Wrong register used to check pending traffic
The incorrect register offset is passed to pci_wait_for_pending(), which is
caused by commit 157e876ffe ("PCI: Add pci_wait_for_pending() (refactor
pci_wait_for_pending_transaction())").
projects / karo-tx-linux.git / log