Robin Gong [Mon, 26 Nov 2012 03:23:28 +0000 (11:23 +0800)]
ENGR00234685-1 cpufreq:fix one bug in cpufreq driver if I2C transfer error
Currently, if we used LDO bypass, will set pfuze register by I2C bus to modify
voltage according to different cpu frequency, if I2C transfer error, we should
restore to old cpu frequency, not only in cpufreq driver but also cpufreq core.
Ge Lei [Fri, 23 Nov 2012 06:36:04 +0000 (14:36 +0800)]
ENGR00233569 SDMA: Add support for SDMA M2M copy
Our SDMA code did not support SDMA M2M copy function before, we add
SDMA M2M copy function in this patch, you can use 'sg' to use this
function, you can refer to 'linux-test/module_test/mxc_sdma_memcopy_test.c'
for how to use this function.
Ryan QIAN [Thu, 22 Nov 2012 07:38:46 +0000 (15:38 +0800)]
ENGR00234519 mmc: support eMMC v4.5 memory cards
Bypass eMMC version checking, so that eMMC v4.5 can work on current kernel as
eMMC v4.4 cards, no specific v4.5 feature supported. Only basic read/write
operations are supported, also ddr mode is supported.
Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com>
Sheng Nan [Fri, 23 Nov 2012 02:59:22 +0000 (10:59 +0800)]
ENGR00234362 Camera: ov5640_mipi: wait for sensor stable before streamon
ov5642 add some delay to wait for sensor stable after S_PARM.
And ov5640_mipi should keep the same behavior.
So the upper layer can trust the first frame comes out of ov5640_mipi.
- delay added according to the recommended time from ov company
Steve Cornelius [Tue, 20 Nov 2012 23:21:26 +0000 (16:21 -0700)]
ENGR00234401: CAAM: Fix incorrect invalidate call for output ring
The job ring driver exhibited a hang condition in the top of
caam_jr_dequeue() where a BUG_ON statement looks for a condition
where the output ring is said to have valid entries by the ring logic,
but the ring entries apparently have NULL descriptor pointers.
In the initial ARM port of this driver, the cache flush call
of the output ring content occured before the output ring read index
register read occurred, exposing a condition where the driver sensed valid
output entries, yet the entries written by the ring hardware were not
invalidated, and therefore were not visible to the processor, appearing
as false NULL entries.
This patch relocates the invalidate call to immediately follow the
check of the output read index, where it is required.
Signed-off-by: Vicki Milhoan <vicki.milhoan@freescale.com> Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Robin Gong [Thu, 22 Nov 2012 05:31:05 +0000 (13:31 +0800)]
ENGR00234411-1 Sabreauto: fix error print COULD NOT SET GP VOLTAGE.
Didn't take more care about non-pfuze board, and there is two place in BSP will
call "mx6_cpu_regulator_init". It means regulator_get will be called twice on
every vddcore/vddsoc regulator. Then one value need set twice ,because from
regulator core view, there is two regulators share the same regulator. The non-
validate one will return error and print "COULD NOT SET GP VOLTAGE!!!!." on
Sabreauto board. The same as Sabrelite and ARM2 board.
Meanwhile, Sabreauto need be configured LDO bypass default. Signed-off-by: Robin Gong <b38343@freescale.com>
Michael Minnick [Tue, 13 Nov 2012 18:51:13 +0000 (12:51 -0600)]
ENGR00233494 EPDC: Driver only supports 16 LUTs
This bug was introduced by ENGR00229290 which fixed
the problem of greater than 16 LUTs used when 5-bit
waveform loaded. The bug is that now the driver is also
restricted to using 16 LUTs in 4-bit mode.
The fix is to correct the test of the EPDC_FORMAT
register used to determine if a 5-bit waveform
is loaded.
Also removed the while loop in favor of a bitwise OR
used to determine if a chosen LUT has yet to be
acknowledged by the interrupt handler.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Robin Gong [Tue, 20 Nov 2012 07:08:12 +0000 (15:08 +0800)]
ENGR00234217 cpufreq:fix loops_per_jiffy wrong on new suspend flow of cpufreq
Currently, we use pm_notifier to enter suspend/resume flow. But in the notifier
we only set cpufreq, didn't tell CPUFREQ core what the current cpufreq setting
now. So in the next time if CPUFREQ core find the current cpu frequncy is not
the value that CPUFREQ core want to set before. CPUFREQ core will force to set
the freqs.old with its own rule, which means the freqs.old will be MODIFYED
unexpectedly, and this will cause wrong loops_per_jiffy. We need add cpufreq_
notify_transition in the suspend/resume interface of cpufreq.
Robby Cai [Mon, 12 Nov 2012 08:17:14 +0000 (16:17 +0800)]
ENGR00229852 csi/v4l: lower the priority of "working queue empty" message
When pause the capture test program, the "working queue empty" message
shows up repeatedly. However this message is expected to show up because
there's no QBUF called. Change pr_err to pr_debug to keep it as debug level.
Robby Cai [Thu, 8 Nov 2012 06:45:56 +0000 (14:45 +0800)]
ENGR00232893 mx6sl: pxp/v4l2: add dependency on CONFIG_FB_MXC_ELCDIF_FB
Without this dependency, we have to manually disable
CONFIG_VIDEO_MXC_PXP_V4L2 when disable CONFIG_FB_MXC_ELCDIF_FB.
Otherwise, a build error shows up. This patch fixed it.
Robin Gong [Mon, 19 Nov 2012 02:04:46 +0000 (10:04 +0800)]
ENGR00233366-4 WDOG LDO_BYPASS: fix wdog2 to reset external pmic in ldo bypass
On Sabresd board design, the WDOG_B output to reset external pmic source from
GPIO_2 pad which can be configured as WDOG2_WDOG_B, so if in ldo bypass mode,
we should use WDOG2 reset signal to reset pmic, not WDOG1. Also, configure the
related pins.
Robin Gong [Tue, 13 Nov 2012 07:06:16 +0000 (15:06 +0800)]
ENGR00233366-2 mx6q_sabresd mx6sl_arm2 mx6sl_evk: config in LDO bypass
U-boot will not care about ldo bypass, move these code from u-boot to kernel.
Move the workaround for PFUZE1.0 to kernel too. Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Mon, 19 Nov 2012 02:21:00 +0000 (10:21 +0800)]
ENGR00233366-1 Anatop PFUZE: LDO bypass can be configed by cmdline
Currently, use CONFIG_MX6_INTER_LDO_BYPASS to enable/disable LDO bypass, and
use the same macro in u-boot too. It's not very friendly ,it will be more
flexible if use dynamic configure by command line input by u-boot.
Two ways to enable LDO bypass:
1. use command line:
You can set "ldo_active=on" or "ldo_active=off" in command line to enable/
disable LDO bypass.
2. set enable_ldo_mode value in board file:
If you didn't set the param in command line, every board
will use its default value, for example, you can find below code in arch/arm/
mach-mx6/mx6q_sabresd_pmic_pfuze100.c:
static int pfuze100_init(struct mc_pfuze *pfuze)
{
....
/*use default mode(ldo bypass) if no param from cmdline*/
if (enable_ldo_mode == LDO_MODE_DEFAULT)
enable_ldo_mode = LDO_MODE_BYPASSED;
....
}
Note:
1.You should know clearly ldo bypass can be only enabled in the board
that mounted with external pmic to supply VDDARM_IN/VDDSOC_IN power rail, and
you should implement related external regulator firstly, such as:
in arch/arm/mach-mx6/board-mx6q_sabresd.c
static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
....
}
otherwise, you have to use internal ldo which is the default configuration.
2.one special case, if the chip is 1.2Ghz, it can't be set LDO bypass.
Robin Gong [Mon, 19 Nov 2012 02:16:22 +0000 (10:16 +0800)]
ENGR00234040 FUSE 1.2G: add fuse bit for 1.2G
Before, we use "arm_freq" in command line to set 1.2G. Now we will read the
fuse bit and "arm_freq", get the mini value to be used as "arm_max_freq".And:
1. you can easily set CPU max freq on what frequency you want by cmdline.
2. if you didn't set arm_freq in cmdline, kernel will read the fuse bit
(0x021bc440) to set the right arm_max_freq.
At the same time, add 1Ghz setpoint if chip max freq is 1.2Ghz.
Jason Liu [Thu, 15 Nov 2012 06:51:10 +0000 (14:51 +0800)]
ENGR00233770 i.mx6q/vpu: Add fuse check for VPU_DISABLE feature
This patch add the fuse check for VPU_DISABLE feature. If the fuse
bit for VPU_DISABLE is 1, which means VPU is disabled, then we will
not register VPU device to the kernel.
ENGR00233705 [MX6SL] -Fix suspend/resume issue when SD1 is used to boot.
Setting certain IOMUX settings on SD1 prevents the system from
entering suspend. These pins are already configured as GPIO, so
it does not help to reconfigure them during suspend.
Terry Lv [Fri, 16 Nov 2012 07:41:01 +0000 (15:41 +0800)]
ENGR00233929: add kernel command line to enable snvs
In MX6Q/DL, originally GPIO_0 is used as CKO pin function. when SNVS
module is enabled, CKO output stops suddenly.
Both CKO clock config register CCOSR and GPIO_0 IOMUX register value are
not changed. But because ALT7 of GPIO_0 pad is SNVS_VIO_5 function. I
doubt that when SNVS module is enabled, GPIO_0 pad is automatically
changed to SNVS instance by SoC.
Thus we add option for snvs enable/disable.
Terry Lv [Thu, 15 Nov 2012 08:50:41 +0000 (16:50 +0800)]
ENGR00233800: CAAM: running sha_speed in cryptodev crashed
The reason is that when switching from SHA1 to SHA256, cryptodev will
create a new session.
But in this new session, the __ctx in allocated req is not fully initialized.
Thus dma_buf in __ctx will be a random value.
If the value is 0 or some address in DMA memory, that will be ok,
otherwise, it will crashed in dma_unmap_single().
The calling sequence is:
ahash_final_ctx=>try_buf_map_to_sec_sg()=>dma_unmap_single()
When calling dma_unmap_single(), the parameter buf_dma is invalid in
crash case.
The error msg is:
kernel BUG at arch/arm/mm/dma-mapping.c:478!
Chen Liangjun [Mon, 12 Nov 2012 05:41:13 +0000 (13:41 +0800)]
ENGR00233780 ASRC: limit output buffer size to avoid kernel dump
For ASRC memory to memory transfer, user would send driver input buffer
and driver would copy converted output buffer into user's buffer.
However, ASRC can't promise the ratio of output buffer size/input buffer
size being equal to output sample rate/input sample rate.e.g, for
convert from 8k to 48k and 1000 bytes input buffer size, ASRC may pop
out 5999 bytes or 6001 bytes. If driver copy all 6001 bytes into user's
buffer, kernel dump may happens cause of accessing unexisted buffer.
In this patch, if ASRC output buffer size is larger than user's buffer
size, discard exact part.
Chen Liangjun [Fri, 16 Nov 2012 02:32:07 +0000 (10:32 +0800)]
ENGR00233886 ASRC: init variable to fix build warning
warning:
Compiling warning on mainline imx_3.0.35 (potential bug):
drivers/mxc/asrc/mxc_asrc.c: In function 'asrc_output_task_worker':
drivers/mxc/asrc/mxc_asrc.c:961:68: warning: 't_size' may be used
uninitialized in this function [-Wuninitialized]
drivers/mxc/asrc/mxc_asrc.c:943:23: note: 't_size' was declared here
Ge Lei [Thu, 15 Nov 2012 06:53:40 +0000 (14:53 +0800)]
ENGR00233570-2 ASRC: Use function pointer and hook to support ASRC loadable
In ASoC pcm platform driver, use function pointer(ASRC ops) and hook to call
the APIs in ASRC driver, so that the ASoC platform driver can support ASRC
loadable.
Ge Lei [Thu, 15 Nov 2012 06:46:19 +0000 (14:46 +0800)]
ENGR00233570-1 ASRC: Use hook to add support for ASRC loadable
ASoC ESAI machine driver and pcm platform driver use the APIs from mxc_asrc.c,
but once ASRC is used as a loadable module, these files can't find the APIs
from this ko. In this patch, we use 'asrc_p2p_hook' to hook the APIs which will
be used in ASoC ESAI machine driver and pcm platform driver.
Nicolin Chen [Thu, 15 Nov 2012 03:28:19 +0000 (11:28 +0800)]
ENGR00233731 ALSA: add DMABUF allocating for different driver
Patch ENGR00233056 added DMABUF size setting for hw_param and changed SSI's
buffer allocating size.
But didn't add allocation for ESAI and SPDIF, which might cause some dma
transmitting issue.
This Patch add new allocation code that detects the driver before allocating
its DMABUF.
Chen Liangjun [Mon, 12 Nov 2012 13:29:32 +0000 (21:29 +0800)]
ENGR00233577 ASRC: add spinlock to protect ASRC pair resource
when quit from ASRC driver with CTRL + C, driver close() would free
output buffer and close clock. However, it is possible that the buffer
is accessed by work task(work task is trigger by interrupt and it would
not be stopped by CTRL + C). So ASRC driver should promise that its
pair resource(buffer, SDMA channel, and clock) would not be accessed
after it is released.
Some board for example sabreauto board usb power gpio is use a io
i2c expander gpio, gpio i2c driver load use subsys_initcall as driver
initialization entry point, so gpio is not accessible at early bootup.
when using DMIX for ALSA playback, ALSA would not update write index
into driver but maintain it in ALSA LIB level. However, HDMI driver
need write index for HDMI header packing. In this case, HDMI driver
would fail to do HDMI header pack and user hear no sound when using DMIX
in HDMI audio playback.
In this patch, use read index(hw_ptr) for HDMI header packing.
make shi [Thu, 8 Nov 2012 07:26:22 +0000 (15:26 +0800)]
ENGR00233051-03 Mx6 USB: msl implementation for USB OTG modulization
- remove mx6_usb_dr_init() in board specific initialization files
- Add module_init(mx6_usb_dr_init) and module_exit(mx6_usb_dr_exit)
in usb_dr.c to support the usb_dr modulization
- Export necessary function which is used in usb_dr.c
make shi [Thu, 8 Nov 2012 07:18:50 +0000 (15:18 +0800)]
ENGR00233051-01 Mx6 USB: configure change for OTG modulization
- Add USB_FSL_ARC_OTG configuration to imx6_defconfig and imx6s_defconfig,
the default configuration is selected as "y"
- add related USB_FSL_ARC_OTG configuration to Makefile
- add related USB_FSL_ARC_OTG configuration to Kconfig
Liu Ying [Tue, 13 Nov 2012 06:42:27 +0000 (14:42 +0800)]
ENGR00233380 IPUv3:Warn on sub-CPMEM EBA0 unalignment case
IPUv3 CPMEM EBA sets buffer start address. EBA should be 8-byte
aligned according to IPUv3 spec. This patch contains code change
only to warn on alternative CPMEM entry's EBA0 unalignment case.
ENGR00224109 - MX6 : FEC : optimize ENET_REF_CLK PAD configuration.
In MX6 Arik and Rigel platforms, RGMII tx_clk clock source is from
ENET_REF_CLK pad supplied by phy. To optimize the clk signal path,
the ENET_REF_CLK I/O must have this configuration:
1. Disable on-chip pull-up, pull-down, and keeper
2. Disable hysteresis
3. Speed = 100 MHz
4. Slew rate = fast
The optimizition make the bias point match the optimum point, which
can maximize design margin.
Michael Minnick [Tue, 6 Nov 2012 19:21:50 +0000 (13:21 -0600)]
ENGR00232660 EPDC: Wrong panel loaded at boot
The wrong EPDC panel can be loaded at boot time if the machine
board file has multiple panel entries with the same video mode
parameter values. To reproduce, select a particular panel with
u-boot kernel command line parameters, for example:
video=mxcepdcfb:XYZZY
Add panel XYZZY to arch/arm/mach-mx6/board-mx6sl_evk.c after
an existing entry. Use the same video mode parameter settings
as the existing entry. On boot, the existing panel will be loaded
instead of the XYZZY panel because it comes earlier in the list
and happens to have the same video mode parameter values.
Solution: If the video mode parameter settings specified in
the call to msc_epdc_fb_set_par() match those of the panel
already loaded by mxc_epdc_fb_probe(), don't execute a
search for a new matching panel.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Sandor Yu [Thu, 8 Nov 2012 08:24:10 +0000 (16:24 +0800)]
ENGR00232930 Added default video mode check, make sure it is a CEA mode.
When system bootup without HDMI plugin, the default modelist
and default video mode will create.
Match default video mode in default CEA modelist, make sure
default video mode is a CEA mode.
Ryan QIAN [Fri, 26 Oct 2012 02:13:34 +0000 (10:13 +0800)]
ENGR00231273-02 mmc: sdhci: fix failed to call platform exit on removal
Since sdhci_pltfm_data is stored in platform_device_id, but in
sdhci_pltfm_remove, it tried to get sdhci_pltfm_data directly from
pdev->dev.platform_data. It will result that it could not get the correct
sdhci_pltfm_data, so that platform exit will not be called on sdhci module's
removal.
Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com>
make shi [Tue, 6 Nov 2012 07:52:24 +0000 (15:52 +0800)]
ENGR00232583 Mx6 USB host: Set HCD_FLAG_HW_ACCESSIBLE flag after clock gate
There is a USB hang issue when do system suspend/resume test with a USB
device plug in. The issue is caused by USB host driver accessing register
when clock is off. Currently set HCD_FLAG_HW_ACCESSIBLE bit before open
clock in ehci_fsl_bus_resume, it cause accessing register without clock.
So we should change the code call order to avoid driver access register
without clock.
- Set HCD_FLAG_HW_ACCESSIBLE software flag after HW clock turn on
- remove some unnecessary code in ehci_fsl_pre_irq
Anson Huang [Tue, 6 Nov 2012 22:47:26 +0000 (17:47 -0500)]
ENGR00232586 mx6: increase PUPSCR to make sure LDO is ready for resume
Previous setting of PUPSCR is 0x202, which means there is only ~63us
for LDO ramp up, sometimes, system fail to resume by USB remote wake up,
increase this timing to fix USB remote wake up issue.
Adrian Alonso [Thu, 25 Oct 2012 20:15:26 +0000 (15:15 -0500)]
ENGR00231266-3: adv7280_mipi_tvin add regulator support
* Add regulator support
Set regulator voltage and enable them
On remove callback disable regulators
* Add callbacks for target platform custom
reset, power up/down and io pads configuration
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Wed, 24 Oct 2012 16:37:11 +0000 (11:37 -0500)]
ENGR00231266-2: adv7280_mipi_tvin add i2c dummy client for csi config
* Add i2c dummy client for csi-tx register map config
* adv7280 csi-tx reg banks are mapped in a different
memory map and respond to a different i2c slave address
that user can configure
* Add default config helper function
* Override slave csi-tx address if user provides a different
value.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Chen Liangjun [Wed, 31 Oct 2012 09:27:23 +0000 (17:27 +0800)]
ENGR00231773-8 ASRC: prevent user app from processing input/output processing
To finish a buffer convert in ASRC, user should 1. prepare input buffer,
2. prepare output buffer 3. wait for output buffer's completion 4.wait
for input buffer's comletion. The flow make user application ugly.
In this patch, pack steps above to 1 stop: ASRC_CONVERT.
When SDMA is use for periphal data transfer, dma request is trigger by
FIFO level. If the SDMA is started after the start of periphal, SDMA
would miss the first pulse and be not able to trigger itself.
In this patch, add interface to trigger a dma request manully.
Chen Liangjun [Wed, 31 Oct 2012 03:11:26 +0000 (11:11 +0800)]
ENGR00231773-5 ASRC: use poll mode to receive last period of ASRC data
ASRC driver use DMA to transfer data from ASRC output FIFO to memory.
However, DMA way require the data number in ASRC output FIFO being larger
than watermark level. Thus a dma request can trigger a DMA burst. For
the last period of output data, its number is possiblely less than output
FIFO watermark level. In this case, the output DMA would pending for the
last period of output data until timeout.
In this patch:
1 divide expected output data length into 2 parts: DMA part
and poll part. Using DMA to get the DMA part data and poll mode to
get the poll part.
2 to prevent user from processing these 2 parts above, kernel
buffers would be untouchable. User application only need send its data
buffer address to driver instead of query the kernel buffer.
Chen Liangjun [Fri, 26 Oct 2012 09:43:30 +0000 (17:43 +0800)]
ENGR00231773-4 ASRC: use scatter list and stall bit for asrc convert
In the origin code, ASRC driver use cyclic way to process DMA task
transfering data to/from ASRC input/output FIFO. In this case, it is
necessary that user application should promise that the input buffer
flow is continuous. If not, there would be 0 data be inserted into data
flow. The output data would be noisy.
In this patch,
1 use scatter list instead of cyclic SDMA: with scatter list,
SDMA would stop when the applied scatter list nents are finished.
2 set stall bit for ASRC "memory->ASRC->memory" convert to stop
ASRC convert when input data is not send into ASRC input FIFO in time.
Chen Liangjun [Fri, 26 Oct 2012 07:10:09 +0000 (15:10 +0800)]
ENGR00231773-3 ASRC: use kzalloc to allocate buffer to support scatterlist
For ASRC's "memory -> ASRC -> memory" using, new driver would support
model below: user input one buffer into ASRC and an corresponding output
buffer would be poped out. There is no timing requirement between this
input buffer and next input buffer. Thus driver would not use the cyclic
way to config SDMA and scatterlist is used. buffer allocated by
dma_alloc_coherent() can't support scatterlist well.
In this patch, use kzalloc to allocate buffer to support scatterlist.
Chen Liangjun [Fri, 26 Oct 2012 05:42:35 +0000 (13:42 +0800)]
ENGR00231773-2 ASRC: add work struct for asrc output data receive
SDMA driver can't promise receive all output data generated. Cause when
the data in output FIFO is less than ASRC output FIFO watermark, there
would be no DMA request generated and thus no SDMA transfer would
happens.
In this patch, add work struct to support ASRC driver receive last part
of data in OUTPUT FIFO in polling way.
Chen Liangjun [Fri, 26 Oct 2012 08:07:41 +0000 (16:07 +0800)]
ENGR00231773-1 ASRC: remove queue operation in ASRC driver
According to ASRC memory->ASRC->memory requirement, driver should
satisfy the feature below: user application would passed into one buffer
and waiting until the output buffer is generated. In this case, only one
buffer is on processing and it is no necessary to use the queue to do
the convert. What is worse, queue operation would make the ASRC driver
hard to understand and maintain.
In this patch, remove the queue operation in ASRC driver.
IPG_PERCLK is the parent of I2C. I2C needs a minimum of
12.8MHz as its input clock to achieve 400KHz speed. Hence
change the IPG_PERCLK speed accordingly.
MX6DQ/MX6DL - Set IPG_PERCLK at 22MHz (sourced from IPG_CLK)
MX6SL - Set IPG_PERCLK to 24MHz(Sourced from 24MHz XTAL).
Israel Perez [Wed, 31 Oct 2012 22:13:36 +0000 (17:13 -0500)]
ENGR00225875-2 i.MX6Q/Solo Sabreauto Bluetooth H4 fix uart rx timeouts.
Bluetooth H4 protocol is very susceptible to data reception timeouts.
DMA transfer only happen when ICD or AGTIM interrutps are trigger.
ICD only happen when a N idle frames are present on rx line
and rx FIFO is empty.
Meanwhile Aging timer is trigger when data in FIFO was been sitting for a
period of 8 frames.
This patch enable both in order to dispatch data as fast is possible only
when the select uart have enable DMA flag.
Signed-off-by: Israel Perez <B37753@freescale.com>
Israel Perez [Wed, 31 Oct 2012 22:06:44 +0000 (17:06 -0500)]
ENGR00225875-1 i.MX6Q/Solo SabreAuto Infineon Bluetooth uart3 config
Configure MUX settings for bluetooth operation over UART3.
Enable RTS,CTS and DMA only for uart3.
Affected files :
arch/arm/mach-mx6/board-mx6q_sabreauto.c
arch/arm/mach-mx6/board-mx6q_sabreauto.h
arch/arm/mach-mx6/board-mx6solo_sabreauto.h
arch/arm/plat-mxc/include/mach/iomux-mx6q.h
On behalf of Francisco Munoz <francisco.munoz@freescale.com>.
Some modification are needed also on hciattach tool.
Signed-off-by: Israel Perez <B37753@freescale.com>
Robby Cai [Fri, 2 Nov 2012 07:58:40 +0000 (15:58 +0800)]
ENGR00232000: Fix "dmaengine: failed to get dma1chan0: (-22)" when boot
The log from [MX6DL/S_SD]:
...
mxc_sdc_fb mxc_sdc_fb.1: register mxc display driver ldb
dmaengine: failed to get dma1chan0: (-22)
dmaengine: failed to get dma1chan1: (-22)
dmaengine: failed to get dma1chan2: (-22)
dmaengine: failed to get dma1chan3: (-22)
dmaengine: failed to get dma1chan4: (-22)
dmaengine: failed to get dma1chan5: (-22)
dmaengine: failed to get dma1chan6: (-22)
dmaengine: failed to get dma1chan7: (-22)
dmaengine: failed to get dma1chan8: (-22)
dmaengine: failed to get dma1chan9: (-22)
dmaengine: failed to get dma1chan10: (-22)
dmaengine: failed to get dma1chan11: (-22)
dmaengine: failed to get dma1chan12: (-22)
dmaengine: failed to get dma1chan13: (-22)
dmaengine: failed to get dma1chan14: (-22)
dmaengine: failed to get dma1chan15: (-22)
...
It happens when there are many DMA-engine drivers in the system and
dmaengine_get() is called. dmaengine_get() will call dma_chan_get(), which will
call device_alloc_chan_resources() literally on channels of available dma
drivers unless reach -ENODEV. device_alloc_chan_resources() is implemented
in the individual dma drivers, which could return -EINVAL rather than -ENODEV,
then the above messages print out (doesn't hurt, however).
Indeed, the dmaengine_get() and dmaengine_put() is not needed and thus removed.
Lionel Xu [Wed, 31 Oct 2012 08:40:37 +0000 (16:40 +0800)]
ENGR00231778 MX6 ESAI: Adjust channel support capability of cpu/codec dai
To adjust the channel support capability, codec dai does not support mono
playback and record, while esai dai does, thus making the whole audio
codec only support stereo and above channel playback/record.
When our DDR size is small or reserved memory are large and
the lowmem can cover all the available pages for kernel,
the highmem pages will not be setup. That means the page_pool
for bounce queue can not be create in init_emergency_pool().
And page_pool will stay NULL without initialized.
In the mmc/card/queue.c the blk_queue_bounce_limit()
function will be called in mmc_init_queue() to
initialize the request_queue and it's bounce_gfp.
If we do not define the DMA mask for our platform,
then the BLK_BOUNCE_HIGH (lowmem pfn) will be set
as limit to queue bounce, which means the blk_queue_bounce
will use page_pool to iterate over the bio segment.
Under the circumstances that highmem is not setup,
the page_pool is null, and causes kernel crash.
After set the DMA mask for esdhci device, the page_pool
will not be used to iterate over the bio segment.
Hongzhang Yang [Thu, 1 Nov 2012 11:26:44 +0000 (19:26 +0800)]
ENGR00232087-1 MX6: Enable PU LDO gating.
1. Revert ENGR00231910 Do not disable PU regulator,revert the PU
regulator patch;
2. VPU reset register address is different on MX6 and MX5. It can
fix ENGR00230203 [Android_MX6DL_SD] Gallery: System hang after resume
from suspend during video playback. 20%
Signed-off-by: Hongzhang Yang <Hongzhang.Yang@freescale.com>
for a big nand chip Micron MT29F64G08AFAAAWP(8GB), we got the following wrong
result:
.............................................
"mtd: partition size too small (0)"
.............................................
We can not get any partition.
The "4g(test)" partition triggers a overflow of the "size". The memparse()
returns 4g to the "size", but the size is "unsigned long" type, so a overflow
occurs, the "size" becomes zero in the end.
This patch changes the "size"/"offset" to "unsigned long long" type,
and replaces the UINT_MAX with ULLONG_MAX for macros SIZE_REMAINING and
OFFSET_CONTINUOUS.
Tony LIU [Thu, 1 Nov 2012 02:15:18 +0000 (10:15 +0800)]
ENGR00231965 MX6 USB CV 3.0 test fail
- For USB CV 3.0 test, the gap between the ACK of set_address and
the subsequent setup packet may be very little, say 500us, and
if the latency we handle the ep completion is greater than this
gap, there is no response to the subsequent packet. It will
cause CV test fail
- There is another way to set the address, it should set the bit 24
to 1 with the right address, and then IC controller will set the
address when the IN req complete instead of SW do it. It is more
fast so it can fix the CV 3.0 test fail issue
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Matthieu CASTET [Mon, 19 Mar 2012 14:35:25 +0000 (15:35 +0100)]
mtd: support ONFI multi lun NAND
With onfi a flash is organized into one or more logical units (LUNs).
A" logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Robin Gong [Wed, 31 Oct 2012 13:41:16 +0000 (21:41 +0800)]
ENGR00231910 PU regulator: do not disable PU regulator
If system enter suspend/resume during VPU encoding on Rigel, there will be
"VPU blocking: timeout." error . But there is ok if enter suspend/resume
during VPU decoding and enter suspend/resume during encoding/decoding on
Arik, until now we didn't know the root cause, so revert it firstly.
Because the previous patch about PU regulator is composed with four commits
and hard to revert, now we adopt simplest way that do not disable PU regulator
in low level. The negative impact is there will several mA increasment in
suspend, we will fix it ASAP. Signed-off-by: Robin Gong <b38343@freescale.com>
Alejandro Sierra [Wed, 24 Oct 2012 20:32:37 +0000 (15:32 -0500)]
ENGR00231063 Sabreauto: fix share pins SD Card and NFC
SD card card detection and NFC controller CS2 share
the same pin on ARD platform. However CS2 is not
connected to the socket. This signal was removed
from the sabreauto board file.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
Steve Cornelius [Fri, 19 Oct 2012 21:43:41 +0000 (14:43 -0700)]
ENGR00230538-5: CAAM: Add SM register defs
Add SM register defs, and expanded driver-private storage.
These add changes to the driver private areas for the CAAM
controller and CAAM Secure Memory subsystems, and expand register
definitions to include the Secure Memory subsystems as reflected
in multiple areas (controller, rings, secure memory itself).
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Steve Cornelius [Fri, 19 Oct 2012 20:27:24 +0000 (13:27 -0700)]
ENGR00230538-2: CAAM: Add Secure Memory and SNVS properties
Add Secure Memory and SNVS properties to MX6 configuration.
Previous configurations of MX6 platform device definition lacked
specific propeties for CAAM Secure Memory and SNVS. Added these
properties to define register ranges for both entities.
Also corrected the name for the offset of the address range for
CAAM Secure Memory to more accurately reflect it's purpose.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Steve Cornelius [Fri, 19 Oct 2012 20:18:37 +0000 (13:18 -0700)]
ENGR00230538-1: CAAM: Correct shifting offset for CAAM IPG clock selection
3 pairs of clock enable bits are required for CAAM clocking:
(1) wrapper IPG clock
(2) wrapper ACLK
(3) secure memory clock
IPG enable happened to be using an incorrect shift selection, which
had the net effect of leaving secure memory unclocked. Added the correct
shift selection in so that all 3 clock enable pairs are turned on.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
Robin Gong [Fri, 26 Oct 2012 11:19:43 +0000 (19:19 +0800)]
ENGR00230981-3 pfuze: add suspend voltage set interface
Implement set_suspend_voltage for buck switch of PF100, and set_suspend_enable
/set_suspend_disable interface for LDO(VGENx). Signed-off-by: Robin Gong <b38343@freescale.com>
projects / karo-tx-linux.git / log