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11 years agoENGR00182346-2 serial: unregister the console when the console is released
Huang Shijie [Wed, 9 May 2012 06:00:57 +0000 (14:00 +0800)]
ENGR00182346-2 serial: unregister the console when the console is released

The old code does not unregister the console mxc_early_uart_console when
it is disabled. This may causes the global console `console_drivers` still
pointes an invalid console mxc_early_uart_console. A hung will be observed
in this situation.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00182346-1 serial/imx : disable the clock when the uart is not used
Huang Shijie [Wed, 9 May 2012 03:36:29 +0000 (11:36 +0800)]
ENGR00182346-1 serial/imx : disable the clock when the uart is not used

This patch is just the re-revert of the commit:ENGR00182048

Disable the clock when the uart port is not used.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00182220 WM8962: set a default volume
Gary Zhang [Wed, 9 May 2012 03:34:37 +0000 (11:34 +0800)]
ENGR00182220 WM8962: set a default volume

set default volume for headphone and speaker

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoimx: add polled io uart methods
Saleem Abdulrasool [Thu, 22 Dec 2011 08:57:53 +0000 (09:57 +0100)]
imx: add polled io uart methods

These methods are invoked if the iMX uart is used in conjuction with kgdb during
early boot.  In order to access the UART without the interrupts, the kernel uses
the basic polling methods for IO with the device.  With these methods
implemented, it is now possible to enable kgdb during early boot over serial.

Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
CC: Sascha Hauer <s.hauer@pengutronix.de>
CC: Fabio Estevam <festevam@gmail.com>
CC: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
CC: linux-serial@vger.kernel.org
CC: Alan Cox <alan@linux.intel.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
11 years agoimx: Add save/restore functions for UART control regs
Dirk Behme [Thu, 22 Dec 2011 08:57:52 +0000 (09:57 +0100)]
imx: Add save/restore functions for UART control regs

Factor out the uart save/restore functionality instead of
having the same code several times in the driver.

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
CC: Saleem Abdulrasool <compnerd@compnerd.org>
CC: Sascha Hauer <s.hauer@pengutronix.de>
CC: Fabio Estevam <festevam@gmail.com>
CC: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
CC: linux-serial@vger.kernel.org
CC: Alan Cox <alan@linux.intel.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
11 years agosched: Cleanup cpu_active madness
Peter Zijlstra [Thu, 15 Dec 2011 16:09:22 +0000 (17:09 +0100)]
sched: Cleanup cpu_active madness

Stepan found:

CPU0 CPUn

_cpu_up()
  __cpu_up()

boostrap()
  notify_cpu_starting()
  set_cpu_online()
  while (!cpu_active())
    cpu_relax()

<PREEMPT-out>

smp_call_function(.wait=1)
  /* we find cpu_online() is true */
  arch_send_call_function_ipi_mask()

  /* wait-forever-more */

<PREEMPT-in>
  local_irq_enable()

  cpu_notify(CPU_ONLINE)
    sched_cpu_active()
      set_cpu_active()

Now the purpose of cpu_active is mostly with bringing down a cpu, where
we mark it !active to avoid the load-balancer from moving tasks to it
while we tear down the cpu. This is required because we only update the
sched_domain tree after we brought the cpu-down. And this is needed so
that some tasks can still run while we bring it down, we just don't want
new tasks to appear.

On cpu-up however the sched_domain tree doesn't yet include the new cpu,
so its invisible to the load-balancer, regardless of the active state.
So instead of setting the active state after we boot the new cpu (and
consequently having to wait for it before enabling interrupts) set the
cpu active before we set it online and avoid the whole mess.

Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1323965362.18942.71.camel@twins
Signed-off-by: Ingo Molnar <mingo@elte.hu>
11 years agoARM: fix rcu stalls on SMP platforms
Russell King [Thu, 19 Jan 2012 15:20:58 +0000 (15:20 +0000)]
ARM: fix rcu stalls on SMP platforms

We can stall RCU processing on SMP platforms if a CPU sits in its idle
loop for a long time.  This happens because we don't call irq_enter()
and irq_exit() around generic_smp_call_function_interrupt() and
friends.  Add the necessary calls, and remove the one from within
ipi_timer(), so that they're all in a common place.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
11 years agoARM: smpboot: Enable irqs on secondary CPU after marking it online/active
Thomas Gleixner [Sat, 15 Oct 2011 00:22:43 +0000 (17:22 -0700)]
ARM: smpboot: Enable irqs on secondary CPU after marking it online/active

Patch is the last version from tglx on Oct 7.

Discussion is at: http://comments.gmane.org/gmane.linux.ports.arm.kernel/131919

The original commit message for the first patch version:

Frank Rowand reported:

 I have a consistent (every boot) hang on boot with the RT patches.
 With a few hacks to get console output, I get:

  rcu_preempt_state detected stalls on CPUs/tasks

 I have also replicated the problem on the ARM RealView (in tree) and
 without the RT patches.

 The problem ended up being caused by the allowed cpus mask being set
 to all possible cpus for the ksoftirqd on the secondary processors.
 So the RCU softirq was never executing on the secondary cpu.

 The problem was that ksoftirqd was woken on the secondary processors before
 the secondary processors were online. This led to allowed cpus being set
 to all cpus.

   wake_up_process()
      try_to_wake_up()
         select_task_rq()
            if (... || !cpu_online(cpu))
               select_fallback_rq(task_cpu(p), p)
                  ...
                  /* No more Mr. Nice Guy. */
                  dest_cpu = cpuset_cpus_allowed_fallback(p)
                     do_set_cpus_allowed(p, cpu_possible_mask)
                        #  Thus ksoftirqd can now run on any cpu...
</report>

The reason is that the ARM SMP boot code for the secondary CPUs enables
interrupts before the newly brought up CPU is marked online and
active.

That causes a wakeup of ksoftirqd or a wakeup of any other kernel
thread which is affine to the brought up CPU break that threads
affinity and therefor being scheduled on already online CPUs.

This problem has been observed on x86 before and the only solution is
to mark the CPU online and wait for the CPU active bit before the
point where interrupts are enabled.

Change-Id: If948ef52d434191579e1ca95d18d0c50e91a03b9
Signed-off-by: Dima Zavin <dima@android.com>
11 years agoENGR00182243 [MX6]Fix suspend/resume issue
Anson Huang [Tue, 8 May 2012 07:10:16 +0000 (15:10 +0800)]
ENGR00182243 [MX6]Fix suspend/resume issue

When there is pending wake up source before SOC enter DSM,
we should restore DDR IO and enable cache then return. Previous
code break r2 register which keep the iram stack addr, will
lead to DDR IO restore fail, need to avoid it.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00182245 Increase gpu mmu handling size to 2G
Loren Huang [Tue, 8 May 2012 07:31:07 +0000 (15:31 +0800)]
ENGR00182245 Increase gpu mmu handling size to 2G

This change can avoid gpu to access invalid address.

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00181670 V4L2: Fix bug:when ubuntu start up, print some fb error messages
Wayne Zou [Mon, 7 May 2012 08:57:30 +0000 (16:57 +0800)]
ENGR00181670 V4L2: Fix bug:when ubuntu start up, print some fb error messages

If only called mxc_vout_open/mxc_vout_release, fb_smem_len are uninitialized.
When ubuntu start up, print some error messages:

mxc_sdc_fb mxc_sdc_fb.1: Unable to allocate framebuffer memory
mxc_v4l2_output mxc_v4l2_output.0: ERR: fb_set_var.
mxc_sdc_fb mxc_sdc_fb.0: Unable to allocate framebuffer memory
mxc_v4l2_output mxc_v4l2_output.0: ERR: fb_set_var.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00180686 [CPUFreq]Delay interactive governor to speed up kernel boot
Anson Huang [Mon, 7 May 2012 01:48:22 +0000 (09:48 +0800)]
ENGR00180686 [CPUFreq]Delay interactive governor to speed up kernel boot

Interactive governor is too early to start, and kernel boot
up speed is impacted, use late_initcall instead of fs_initcall.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00182054: [MX6]: always_present flag will't work as designed at some cond
Ryan QIAN [Mon, 7 May 2012 05:54:04 +0000 (13:54 +0800)]
ENGR00182054: [MX6]: always_present flag will't work as designed at some cond

As designed, when 'always_present' is set, it is assumed that cd_gpio should
be not set, and gpio_get_value(boarddata->cd_gpio) should return 0. But it is
not sure that the return value of gpio_get_value(0) is 0.

- check always_present first
- remove ESDHC_FLAG_GPIO_FOR_CD_WP flag if always_present is set.

Signed-off-by: Ryan QIAN <b32804@freescale.com>
11 years agoENGR00179636-04 - FEC : allocate the enough DMA size for BD.
Fugang Duan [Mon, 7 May 2012 07:14:23 +0000 (15:14 +0800)]
ENGR00179636-04 - FEC : allocate the enough DMA size for BD.

- Increase RX BD size to 384 entrys from 16 entrys, and allocate
  the enough DMA memory for buffer description.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00180497 FB: Fix a bug: 'fb_set_par error, -22' when video playback on lvds
Wayne Zou [Mon, 7 May 2012 04:47:30 +0000 (12:47 +0800)]
ENGR00180497 FB: Fix a bug: 'fb_set_par error, -22' when video playback on lvds

Change bg_id/fg_id variable to char array variable, and
avoid change the constant string in .rodata section.

[MX6Q SMD]fb: 'fb_set_par error, -22' prompted when mplay a video to lvds
/mnt/nfs/util/mplayer /mnt/nfs/test_stream/video/Mpeg4_SP1_1280x720_30fps.mp4
Before video playback finish, fb error message shows:

mxc_sdc_fb mxc_sdc_fb.0: setup error, dispdrv:ldb.
detected fb_set_par error, error code: -22
Can't reset original fb_var_screeninfo: Invalid argument
Exiting... (End of file)

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00182048: Revert "ENGR00175578 serial/imx..."
Jason Liu [Mon, 7 May 2012 03:25:17 +0000 (11:25 +0800)]
ENGR00182048: Revert "ENGR00175578 serial/imx..."

This reverts commit a7d9c8864ab801920f6a630767656f6777a95de2.

This commit will break i.mx6dl boot up on SD board and hang at:
Bus freq driver loaded...

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00181094-5: MAX8903: modify dirver and free gpio resource in gpio err.
Rong Dian [Fri, 4 May 2012 09:44:11 +0000 (17:44 +0800)]
ENGR00181094-5: MAX8903: modify dirver and free gpio resource in gpio err.

1.free gpio in request gpio err.

2.in driver probe,directly set the type of power supply AC.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00181068: MX6 Source IPU_HSP and AXI clocks from 540M PFD.
Ranjani Vaidyanathan [Thu, 26 Apr 2012 22:53:14 +0000 (17:53 -0500)]
ENGR00181068: MX6 Source IPU_HSP and AXI clocks from 540M PFD.

IPU_HSP clocks should NOT be sourced from MMDC clock since the
MMDC clock can be scaled.
Move the IPU_HSP clock to be sourced from PLL3_PFD_540M instead.
Also don't source AXI_CLK from periph_clk as this domain is
scaled between 528MHz, 400MHz and 24MHz. Move AXI_CLK
clock to be sourced from PLL3_PFD_540M too.

When the system needs to enter low power mode, AXI_CLK is switched
from PLL3_PFD_540M to periph_clk. And then switched back
when low power mode is exited.

The code will print a warning message if PLL3_PFD_540M is
relocked to a different frequency when IPU_HSP or axi_clk is
sourced from it.

Currently remove the support for 400Mhz DDR working point for
MX6Q since we can get IPU underruns during the DDR frequency
transitions.

The DDR freq change code needs to ensure that all bus clocks
donot exceed max frequency during the frequency transition.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00181514 - FEC : fix kernel dump warning with suspend/resume.
Fugang Duan [Fri, 4 May 2012 07:48:42 +0000 (15:48 +0800)]
ENGR00181514 - FEC : fix kernel dump warning with suspend/resume.

- Fix clock enable/disable match operation to avoid kernel
  dump warning "clock enable/disable mismatch".

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00181697 HDMI: fix ahb bus error bug
Chen Liangjun [Fri, 4 May 2012 09:49:51 +0000 (17:49 +0800)]
ENGR00181697 HDMI: fix ahb bus error bug

In ARIK, to prevent noise cause by false triggered burst, we reduce
the incr type to 4. and the change may cause bus_error because a
burst may unexpectly stop and thus an AHB bus error happens.

Reset HDMI Audio FIFO state to prevent AHB bus error.
Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00181693 HDMI:threshold and INCR type config
Chen Liangjun [Fri, 4 May 2012 09:30:13 +0000 (17:30 +0800)]
ENGR00181693 HDMI:threshold and INCR type config

Configure information for threshold and incr:

CHIP + CHANNEL      THRESHOLD     INCRTYPE
      ARIK + 2            126            4
  ARIK + 4,6,8            124            4
RIGEL + 2,4,6,8           128            8

Signed-off-by: Chen Liangjun <b36089@freescale.com>
11 years agoENGR00181348-2 :sabresd pfuze support cpu internal LDO bypass
Robin Gong [Wed, 2 May 2012 07:36:49 +0000 (15:36 +0800)]
ENGR00181348-2 :sabresd pfuze support cpu internal LDO bypass

1. need  add flag to let cpu freq driver know pfuze regulator is ok or not
,so that cpu freq driver can directly used, otherwise cpu freq should use
raw i2c write/read interface.
2. fix one build warning
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00181348-1 :sabresd pfuze support cpu internal LDO bypass
Robin Gong [Thu, 3 May 2012 10:11:06 +0000 (18:11 +0800)]
ENGR00181348-1 :sabresd pfuze support cpu internal LDO bypass

VDDCORE output directly from pfuze not internal anatop regulator,VDDCORE can
be adjust by pfuze regulator with deifferent cpu frequency, these patch should
be used with u-boot related patch, because LDO bypass is set on u-boot. u-boot
and kernel can be configured by CONFIG_MX6_INTER_LDO_BYPASS, by default it is
disabled, can be used on RevC. These code is put in arch/arm.
Signed-off-by: Robin Gong <B38343@freescale.com>
11 years agoENGR00181094-4: MAX8903: improve battery charger driver
Rong Dian [Thu, 3 May 2012 12:08:50 +0000 (20:08 +0800)]
ENGR00181094-4: MAX8903: improve battery charger driver

1.change the battery driver's name to sabresd_battery.c ,it
means this driver is only special for sabersd boards.

2.fix battery charger function bugs and improve driver code.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00181094-3: MX6 SABRESD: remove MAX8903 interrupt pin config
Rong Dian [Thu, 3 May 2012 12:04:27 +0000 (20:04 +0800)]
ENGR00181094-3: MX6 SABRESD: remove MAX8903 interrupt pin config

move max8903 interrupt pin config from board-mx6q_sabresd.c into
sabresd_battery driver on SABRESD_rev.B board.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00181518 MAX11801: remove unnecessary debug information
Rong Dian [Thu, 3 May 2012 07:59:31 +0000 (15:59 +0800)]
ENGR00181518 MAX11801: remove unnecessary debug information

remove unnecessary debug information e.g.,aux: bd8.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00181548 ov5640 mipi: fix VGA QVGA 15fps no output frame from sensor
Yuxi Sun [Thu, 3 May 2012 08:25:59 +0000 (16:25 +0800)]
ENGR00181548 ov5640 mipi: fix VGA QVGA 15fps no output frame from sensor

There are no output frame from sensor when set to those two mode at
15fps, so, modify these setting of the two mode.

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00181196-2 ov5642: fix the first frame of capture quality is bad
Yuxi Sun [Thu, 3 May 2012 03:03:21 +0000 (11:03 +0800)]
ENGR00181196-2 ov5642: fix the first frame of capture quality is bad

Add 300ms delay after intial setting is download

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00181196-1 ov5640: fix the first frame of capture quality is bad
Yuxi Sun [Thu, 3 May 2012 02:40:18 +0000 (10:40 +0800)]
ENGR00181196-1 ov5640: fix the first frame of capture quality is bad

Add 300ms delay after download the inital setting

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00180530 ov5640 mipi: Add gain calculation and stream on/off in setting
Yuxi Sun [Wed, 2 May 2012 07:13:43 +0000 (15:13 +0800)]
ENGR00180530 ov5640 mipi: Add gain calculation and stream on/off in setting

Using steam on/off to prevent sensor from no frame come out sometimes,
and gain calculation is used to help conquer green color when take picture
at QSXGA.

Also add QCIF resolution for 15/30 fps in this patch.

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00174928 LDB: Check for disp_id for LDB_SIN0/1 mode
Wayne Zou [Wed, 2 May 2012 06:40:59 +0000 (14:40 +0800)]
ENGR00174928 LDB: Check for disp_id for LDB_SIN0/1 mode

For LDB_SIN0 mode, lvds channel0 can only connect with ipu di0
For LDB_SIN1 mode, lvds channel1 can only connect with ipu di1

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00178630-2 MX6DL SabreSD: Add enable_lcd_ldb cmdline option for LVDS+WVGA
Wayne Zou [Wed, 2 May 2012 06:59:01 +0000 (14:59 +0800)]
ENGR00178630-2 MX6DL SabreSD: Add enable_lcd_ldb cmdline option for LVDS+WVGA

Add enable_lcd_ldb command line option for dual display
with LVDS and WVGA LCD panel together on MX6DL.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00178630-1 MX6Q/DL SabreSD:Remove disable_ldb command line option
Wayne Zou [Wed, 2 May 2012 05:18:30 +0000 (13:18 +0800)]
ENGR00178630-1 MX6Q/DL SabreSD:Remove disable_ldb command line option

Since the ldb clock source is different from mipi display,
it doesn't need this option.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00175578 serial/imx : disable the clock when the uart is not used
Huang Shijie [Wed, 2 May 2012 07:48:45 +0000 (15:48 +0800)]
ENGR00175578 serial/imx : disable the clock when the uart is not used

Disable the clock when the uart port is not used.

Signed-off-by: Huang Shijie <b32955@freescale.com>
11 years agoENGR00181323 update pixel clock name in HDMI Audio driver
Sandor Yu [Wed, 2 May 2012 07:23:28 +0000 (15:23 +0800)]
ENGR00181323 update pixel clock name in HDMI Audio driver

update pixel clock name in HDMI Audio driver

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agommc_block: Allow more than 8 partitions per card
Colin Cross [Fri, 3 Sep 2010 19:41:21 +0000 (12:41 -0700)]
mmc_block: Allow more than 8 partitions per card

Set the GENHD_FL_EXT_DEVT flag, which will allocate minor numbers
in major 259 for partitions past disk->minors.

Also remove the use of disk_devt to determine devidx from md->disk.
md->disk->first_minor is always initialized from devidx and can
always be used to recover it.

Signed-off-by: Colin Cross <ccross@android.com>
11 years agoENGR00181201 mx6x HDMI audio add IEC head optimization with C code
Sandor Yu [Sat, 28 Apr 2012 10:55:44 +0000 (18:55 +0800)]
ENGR00181201 mx6x HDMI audio add IEC head optimization with C code

mx6x HDMI audio add IEC head optimization with C code

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00181188 Added miss file hdmi_cpm.S for patch ENGR00181130
Sandor Yu [Fri, 27 Apr 2012 09:18:25 +0000 (17:18 +0800)]
ENGR00181188 Added miss file hdmi_cpm.S for patch ENGR00181130

Added miss file hdmi_cpm.S for patch ENGR00181130

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00181130 Optimizate HDMI audio mmap to fix HDMI audio alsa underrun
Sandor Yu [Wed, 2 May 2012 07:04:00 +0000 (15:04 +0800)]
ENGR00181130 Optimizate HDMI audio mmap to fix HDMI audio alsa underrun

HDMI audio DMA FIFO size is setting to 126, and use INCR4 mode
to fix FIFO overflow issue.
Added Neon code for PCM data IEC head and data copy.

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00181107 add dma_alloc_writethrough function
Sandor Yu [Fri, 27 Apr 2012 09:16:10 +0000 (17:16 +0800)]
ENGR00181107 add dma_alloc_writethrough function

add dma_alloc_writethrough function to dma_mapping.c

Signed-off-by: Sandor Yu <R01008@freescale.com>
11 years agoENGR00181070 Enable SPI NOR on kernel command line
Alejandro Sierra [Mon, 30 Apr 2012 20:17:08 +0000 (15:17 -0500)]
ENGR00181070 Enable SPI NOR on kernel command line

SPI NOR will be enable through spi-nor
command line as a kernel argument

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00180103-3 V4L2: HDMI display error when dual display with LVDS panel
Wayne Zou [Sat, 28 Apr 2012 09:23:50 +0000 (17:23 +0800)]
ENGR00180103-3 V4L2: HDMI display error when dual display with LVDS panel

Restore fb_var_screeninfo when finishing video playback

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00180103-2 V4L2: remove GFP_DMA flag when alloc dma memory
Wayne Zou [Sat, 28 Apr 2012 09:18:19 +0000 (17:18 +0800)]
ENGR00180103-2 V4L2: remove GFP_DMA flag when alloc dma memory

Remove GFP_DMA flag when alloc dma memory.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00180103-1 V4L2: use copy_from/to_user() for user space pointer
Wayne Zou [Sat, 28 Apr 2012 09:13:25 +0000 (17:13 +0800)]
ENGR00180103-1 V4L2: use copy_from/to_user() for user space pointer

V4L2: use copy_from/to_user() for user space pointer

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00181194 IPUv3:Correct pixel clock definition and register
Liu Ying [Sat, 28 Apr 2012 05:24:45 +0000 (13:24 +0800)]
ENGR00181194 IPUv3:Correct pixel clock definition and register

MX6Q has 2 IPUs, each IPU has 2 DIs, so there are totally 4
different pixel clocks. This patch adds maximal pixel clock
number from 2 to 4. Also, the patch fixes potential build
warning caused by the overflow on ipu_lookups structure in case
MXC_IPU_MAX_NUM is 1.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00180943-14: Update internal definition of hardware link table list
Steve Cornelius [Fri, 20 Apr 2012 00:26:40 +0000 (17:26 -0700)]
ENGR00180943-14: Update internal definition of hardware link table list

Update internal definition of hardware link table list such that it can
work properly on both big and little endian 32-bit configurations. This
required pointer resizing, reserved-field initialization, and the
combination of both buffer-pool ID and offset fields into a common
32-bit value that can burst-read correctly.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-13: Extend for ARM/iMX6 compatibility
Steve Cornelius [Wed, 18 Apr 2012 22:09:09 +0000 (15:09 -0700)]
ENGR00180943-13: Extend for ARM/iMX6 compatibility

Extend for ARM/iMX6 compatibility, including:
- Cache coherence for all streaming buffer mappings
- Initialization from non-OF-dependent lower-level drivers

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-12: Extend to include support for ARM targets on iMX6 platforms
Steve Cornelius [Wed, 18 Apr 2012 21:38:50 +0000 (14:38 -0700)]
ENGR00180943-12: Extend to include support for ARM targets on iMX6 platforms

Extend to include support for ARM targets on iMX6 platforms, including:
- platform property detection when OF device properties unavailable
- ring entry direction clarification for DMA API access
- cache coherence for rings

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-11: Add non-device-tree platform property detection
Steve Cornelius [Wed, 18 Apr 2012 21:23:34 +0000 (14:23 -0700)]
ENGR00180943-11: Add non-device-tree platform property detection

Add non-device-tree platform property detection for driver startup and
initialization for iMX6 family, including clock control, job ring
detection and initialization, and interrupt mapping.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-10: Add register I/O primitives for ARM compatibility
Steve Cornelius [Wed, 18 Apr 2012 20:59:05 +0000 (13:59 -0700)]
ENGR00180943-10: Add register I/O primitives for ARM compatibility

Add register I/O primitives for ARM compatibility.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-9: Include referenced for clock control
Steve Cornelius [Wed, 18 Apr 2012 20:50:46 +0000 (13:50 -0700)]
ENGR00180943-9: Include referenced for clock control

Include referenced for clock control,
and define "empty" IRQ function that's not provided on ARM platforms.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-8: Differentiate inclusions for OF versus non-OF platforms
Steve Cornelius [Wed, 18 Apr 2012 20:46:54 +0000 (13:46 -0700)]
ENGR00180943-8: Differentiate inclusions for OF versus non-OF platforms

Differentiate inclusions for OF versus non-OF platforms,
and include clock control subsystems for ARM targets.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-7: Add CAAM device instantiation to iMX platform.
Steve Cornelius [Wed, 18 Apr 2012 20:24:24 +0000 (13:24 -0700)]
ENGR00180943-7: Add CAAM device instantiation to iMX platform.

Add CAAM device instantiation to iMX platform.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-6: Place CAAM Job Ring resources in their own struct
Steve Cornelius [Wed, 18 Apr 2012 18:59:37 +0000 (11:59 -0700)]
ENGR00180943-6: Place CAAM Job Ring resources in their own struct

Place CAAM Job Ring resources in their own struct,
and treat as array to the limit of instantiable rings.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-5: Add CAAM instantiation data to i.MX6 common platform device set
Steve Cornelius [Fri, 23 Mar 2012 17:00:00 +0000 (10:00 -0700)]
ENGR00180943-5: Add CAAM instantiation data to i.MX6 common platform device set

Add CAAM instantiation data to i.MX6 common platform device set.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-4: Add CAAM platform configuration to platform build
Steve Cornelius [Fri, 23 Mar 2012 16:55:02 +0000 (09:55 -0700)]
ENGR00180943-4: Add CAAM platform configuration to platform build

Add CAAM platform configuration to platform build.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-3: Add CAAM instantiation to i.MX6Q ARM2 board platform
Steve Cornelius [Fri, 23 Mar 2012 16:32:01 +0000 (09:32 -0700)]
ENGR00180943-3: Add CAAM instantiation to i.MX6Q ARM2 board platform

Add CAAM instantiation to i.MX6Q ARM2 board platform configuration.
No other device-on-board configurations added at this time.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-2: Enable MXC devices to select CAAM driver in Kconfig
Steve Cornelius [Tue, 13 Mar 2012 21:51:17 +0000 (14:51 -0700)]
ENGR00180943-2: Enable MXC devices to select CAAM driver in Kconfig

Enable MXC devices to select CAAM driver in Kconfig.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
11 years agoENGR00180943-1: Backport in current 3.2 code tested on Power for ARM
Steve Cornelius [Tue, 13 Mar 2012 18:57:50 +0000 (11:57 -0700)]
ENGR00180943-1: Backport in current 3.2 code tested on Power for ARM

Backport in current 3.2 code tested on Power for ARM redevelopment.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400M
Wayne Zou [Fri, 27 Apr 2012 06:31:55 +0000 (14:31 +0800)]
ENGR00181191 MX6: set ipu2_clk parent from pll2_pfd_400M

On mx6dl, set ipu2_clk's parent from pll2_pfd_400M.
On mx6q, ipu2_clk's parent from mmdc_ch0_axi_clk, and it is 264MHz by default.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00181094-2: MAX8903: Add battery charger driver
Rong Dian [Fri, 27 Apr 2012 09:18:54 +0000 (17:18 +0800)]
ENGR00181094-2: MAX8903: Add battery charger driver

Add battery charger driver on SABRESD_rev.B board.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00181094-1: MX6 SABRESD: Add pin config for MAX8903
Rong Dian [Fri, 27 Apr 2012 07:48:59 +0000 (15:48 +0800)]
ENGR00181094-1: MX6 SABRESD: Add pin config for MAX8903

Configure PINMUX for max8903 driver on SABRESD_rev.B board.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00180621-2: mx6dl_sabresd: Add pinmux setting for elan driver
Robby Cai [Tue, 24 Apr 2012 03:39:29 +0000 (11:39 +0800)]
ENGR00180621-2: mx6dl_sabresd: Add pinmux setting for elan driver

Configure PINMUX for ELAN driver on MX6DL SABRESD

Signed-off-by: Robby Cai <R63905@freescale.com>
11 years agoENGR00180621-1: Add ELAN capacity touch screen driver
Robby Cai [Mon, 23 Apr 2012 08:12:20 +0000 (16:12 +0800)]
ENGR00180621-1: Add ELAN capacity touch screen driver

Add Elan ts driver.

Signed-off-by: Robby Cai <R63905@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00180076: prompt "mmc0: error -110 during resume" with atheros wifi card
justin.jiang [Fri, 27 Apr 2012 04:42:29 +0000 (12:42 +0800)]
ENGR00180076: prompt "mmc0: error -110 during resume" with atheros wifi card

* only happend on sabre-auto board,atheros sdio wifi card can't be used
  after suspend/resume

* Fix by keeping sdio power at suspend.

Signed-off-by: justin.jiang <b31011@freescale.com>
11 years agoENGR00180236-2: spdif clk usecount is 1 when not in use
Adrian Alonso [Wed, 25 Apr 2012 23:05:44 +0000 (18:05 -0500)]
ENGR00180236-2: spdif clk usecount is 1 when not in use

* Move spdif_core_clk enable from spdif_probe to spdif_startup
  function in order to avoid initializing the core clock
  when module is not in use.
* At spdif_shutdown disable spdif core_clk.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00180236: mxc_spdif add spdif_clk error check
Adrian Alonso [Wed, 25 Apr 2012 23:03:50 +0000 (18:03 -0500)]
ENGR00180236: mxc_spdif add spdif_clk error check

* Add get_clk clock error check
  abort driver probe if wrong clock.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
11 years agoENGR00180882- MX6DL Add bus frequency scaling support.
Ranjani Vaidyanathan [Thu, 26 Apr 2012 03:31:23 +0000 (22:31 -0500)]
ENGR00180882- MX6DL Add bus frequency scaling support.

Added support for changing DDR frequency on MX6DL.
During system IDLE, DDR freq can drop down to 24MHz
if none of the devices that need high AHB frequency
are active.
Changed the DDR code to handle both MX6Q and MX6DL
DDR and IOMUX settings.
Fixed bug associated incorrect IRAM memory allocation
used to store DDR and IOMUX data.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00175084 IPU-FB: change dma memory alloc gfp flags to GFP_KERNEL
Wayne Zou [Thu, 26 Apr 2012 04:53:52 +0000 (12:53 +0800)]
ENGR00175084 IPU-FB: change dma memory alloc gfp flags to GFP_KERNEL

We only needs the dma buffer, don't care if it is from DMA Zone on i.mx SOC.

To fix the following bug:
mxc_ipudev_test: page allocation failure: order:13, mode:0x1
[<80042e08>] (unwind_backtrace+0x0/0xfc) from [<800b4dd8>]
(warn_alloc_failed+0x9c/0x118)
[<800b4dd8>] (warn_alloc_failed+0x9c/0x118) from [<800b5ac4>]
(__alloc_pages_nodemask+0x494/0x6ec)
[<800b5ac4>] (__alloc_pages_nodemask+0x494/0x6ec) from [<80046154>]
(__dma_alloc+0xd4/0x2fc)
[<80046154>] (__dma_alloc+0xd4/0x2fc) from [<800463a0>]
(dma_alloc_writecombine+0x24/0x2c)
[<800463a0>] (dma_alloc_writecombine+0x24/0x2c) from [<8024be34>]
(mxcfb_set_par+0x3e4/0x4c0)
[<8024be34>] (mxcfb_set_par+0x3e4/0x4c0) from [<80235f08>]
(fb_set_var+0x168/0x2a4)
[<80235f08>] (fb_set_var+0x168/0x2a4) from [<802363f8>](do_fb_ioctl+0x3b4/0x5f0)
[<802363f8>] (do_fb_ioctl+0x3b4/0x5f0) from[<800f58d0>](do_vfs_ioctl+0x80/0x5e4)
[<800f58d0>] (do_vfs_ioctl+0x80/0x5e4) from [<800f5e6c>] (sys_ioctl+0x38/0x60)
[<800f5e6c>] (sys_ioctl+0x38/0x60) from [<8003d500>] (ret_fast_syscall+0x0/0x30)
mxc_sdc_fb mxc_sdc_fb.0: Unable to allocate framebuffer memory
detected fb_set_par error, error code: -12

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00178223-3 gpio-led: Add LED-GPIO control and trigger for sabresd
Lin Fuzhen [Thu, 26 Apr 2012 06:54:44 +0000 (14:54 +0800)]
ENGR00178223-3 gpio-led: Add LED-GPIO control and trigger for sabresd

Add led-gpio control and trigger for sabresd

Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
11 years agoENGR00178223-2 gpio-led: Add LED-GPIO control and trigger for sabresd
Lin Fuzhen [Wed, 25 Apr 2012 05:30:50 +0000 (13:30 +0800)]
ENGR00178223-2 gpio-led: Add LED-GPIO control and trigger for sabresd

Add led-gpio control and trigger for sabresd

Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
11 years agoENGR00178223-1 gpio-led: Add LED-GPIO control and trigger for sabresd
Lin Fuzhen [Wed, 25 Apr 2012 05:26:18 +0000 (13:26 +0800)]
ENGR00178223-1 gpio-led: Add LED-GPIO control and trigger for sabresd

Add led-gpio control and trigger for sabresd

Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
11 years agoENGR00180647-2: MAX11801: Add adc sample function in DCM mode.
Rong Dian [Thu, 26 Apr 2012 07:04:55 +0000 (15:04 +0800)]
ENGR00180647-2: MAX11801: Add adc sample function in DCM mode.

add aux adc sample function in dcm mode
for max11801 driver on SABRESD_rev.B board.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00180647-1: MX6 SABRESD: Add pin config for max11801
Rong Dian [Thu, 26 Apr 2012 07:00:18 +0000 (15:00 +0800)]
ENGR00180647-1: MX6 SABRESD: Add pin config for max11801

Configure PINMUX for max11801 driver on SABRESD_rev.B board.

Signed-off-by: Rong Dian <b38775@freescale.com>
11 years agoENGR00180185: MX6-Add support for low power audio playback
Ranjani Vaidyanathan [Wed, 18 Apr 2012 04:05:43 +0000 (23:05 -0500)]
ENGR00180185: MX6-Add support for low power audio playback

The DDR frequency needs to be at 50MHz for low power audio
playback. So added a new low power mode for audio.
Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this
mode.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
11 years agoENGR00175575 IPU-FB: ldb and hdmi clock is not turnoff when not in use.
Wayne Zou [Wed, 25 Apr 2012 07:22:06 +0000 (15:22 +0800)]
ENGR00175575 IPU-FB: ldb and hdmi clock is not turnoff when not in use.

ldb clock is not turnoff,
ldb_di0_clk's enable_count is not zero when not in use.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00180775 IPUv3:Change pixel clock disabling sequence
Liu Ying [Wed, 25 Apr 2012 06:34:31 +0000 (14:34 +0800)]
ENGR00180775 IPUv3:Change pixel clock disabling sequence

This patch postpones pixel clock and its parent clock(if
the parent clock usecount is 1) disabling time point
until DC/DP/DI enable bits are cleared in IPU_CONF
register to prevent LVDS display channel starvation for
some special LVDS display video mode.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
11 years agoENGR00180099 IPU-[MX6DL]: ipu performance test cause kernel dump
Wayne Zou [Wed, 25 Apr 2012 01:03:52 +0000 (09:03 +0800)]
ENGR00180099 IPU-[MX6DL]: ipu performance test cause kernel dump

1. under vte test environment, boot up and run  ipu_test.sh 7.
kernel dump occur

kernel BUG at drivers/mxc/ipu3/ipu_device.c:1153!

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = 80004000
[00000000] *pgd=00000000
Internal error: Oops: 817 [#1] PREEMPT SMP
Modules linked in: ov3640_camera adv7180_tvin ov5640_camera_mipi
camera_sensor_clock
CPU: 0    Not tainted  (3.0.15-daily-01339-gddc0ae9 #1)
PC is at __bug+0x1c/0x28
LR is at __bug+0x18/0x28
pc : [<80042210>]    lr : [<8004220c>]    psr: 60000013
sp : b41bfc80  ip : c0924000  fp : 00000000
r10: 00000000  r9 : 00000000  r8 : 00000000
r7 : 80a9e0f0  r6 : 80a9e10a  r5 : 00000001  r4 : b46f0800
r3 : 00000000  r2 : 80a4e57c  r1 : 60000093  r0 : 00000038
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c53c7d  Table: 4481404a  DAC: 00000015
Process ipu0_task (pid: 400, stack limit = 0xb41be2f0)
Stack: (0xb41bfc80 to 0xb41c0000)
fc80: 80a9a180 8036fe24 b46f0800 00000000 60000013 b41be000 b46f0800 80373750
fca0: b41bfcd4 80065104 b418aadc 80096598 b418a8ac 60000013 00000000 b418a7e0
fcc0: b41bfcdc b418a7e8 80a4e598 8006a814 b418a7e0 80065268 00000000 00000094
fce0: 00000000 60000013 b41be000 b46f0800 00000000 00000000 00000000 803742e8
fd00: 00000000 b41bfd04 b41bfd04 00000000 00000000 00000000 00000000 00000000
fd20: 00000000 b41be000 00000001 00000000 00000000 b41bfd34 b41bfd34 00000000
fd40: 00000000 00000000 00000001 00000000 00000000 b41bfd54 b41bfd54 00000000
fd60: b41bfd60 b41bfd60 00000000 b4198474 00000000 800f9a34 00000000 800f8f4c
fd80: 00000000 b2000170 b41bfe18 b2001088 80a3bcfc b2000194 b2010bfc b2010bb0
fda0: b41bfeb8 800f86d0 00000000 b41bfe24 b41bfe34 b41bfeb8 00000000 b2000194
fdc0: b2010bb0 00000000 b2001088 800f6e00 b400f0a0 b41bfe18 b2010bb0 b2001088
fde0: b41bfe36 b41bff17 ffffffff b41bff24 b41bfe36 b41bff17 ffffffff b41bff24
fe00: 0000002f b41bff24 00000002 00000003 0000000a ffffffff 00000000 00000000
fe20: 00000000 00000000 b2010bb0 b4114700 b400faa0 39316240 ffffff33 b41be000
fe40: b41be000 b41bff80 00000000 800e69fc 80a3bcc0 8005dc90 80a7b8ec ffffffff
fe60: b4050000 00000002 00000000 80087e2c 00003e80 00000000 b4189998 8c008f90
fe80: 28345a72 b41bfeac 00003e80 00000000 b4189960 8c008f90 b4189960 8c008f90
fea0: 80a7b8ec ffffffff b4126000 00000002 00000000 80087e2c 80a3bcc0 8005dc90
fec0: 0000091d 00000000 b418a818 8c008f90 299c8c15 b41bfefc b418a818 8c008f90
fee0: b418a820 8005c700 00000000 8c008f90 b418a818 b418a818 b41bff14 8005e1d8
ff00: 00000002 8c008f40 b418a7e0 b41be000 b41bffc4 804ba600 8c008f40 b4040000
ff20: b41bff44 8005f920 b4040000 8c008f40 80037f40 80037f40 800371b4 80037f40
ff40: 80037f40 80037f40 800371b4 80037f40 b4189960 b403fe38 80064f14 00000001
ff60: b403fe44 00000000 00000000 00000003 b41bffa4 8005bec0 ffffffff 00000000
ff80: b4040000 00000000 b418a7e0 80082ebc b41bff90 b41bff90 00000031 803741e5
ffa0: 00000013 b403fe28 80a9e138 803741e4 00000013 00000000 00000000 00000000
ffc0: 00000000 80082898 8003fa08 00000000 80a9e138 00000000 00000000 00000000
ffe0: b41bffe0 b41bffe0 b403fe28 80082818 8003fa08 8003fa08 00000000 00000000
[<80042210>] (__bug+0x1c/0x28) from [<8036fe24>] (_get_vdoa_ipu_res+0x23c/0x25c)
[<8036fe24>] (_get_vdoa_ipu_res+0x23c/0x25c) from [<80373750>]
(get_res_do_task+0x10/0x458)
[<80373750>] (get_res_do_task+0x10/0x458) from [<803742e8>]
(ipu_task_thread+0x104/0xa60)
[<803742e8>] (ipu_task_thread+0x104/0xa60) from [<80082898>] (kthread+0x80/0x88)
[<80082898>] (kthread+0x80/0x88) from [<8003fa08>] (kernel_thread_exit+0x0/0x8)
Code: e59f0010 e1a01003 eb11d231 e3a03000 (e5833000)

---[ end trace db719a475f81b6f8 ]---

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00180628 [MX6]L2 cache clean is not necessary in suspend
Anson Huang [Tue, 24 Apr 2012 04:19:29 +0000 (12:19 +0800)]
ENGR00180628 [MX6]L2 cache clean is not necessary in suspend

L2 cache clean is not necessary any more, already tested it on
Arik ARM2, Arik Sabre-SD and Rigel Sabre-SD board.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00180350-2 HDMI set infoframe information
Alan Tull [Wed, 18 Apr 2012 16:40:08 +0000 (11:40 -0500)]
ENGR00180350-2 HDMI set infoframe information

Get speaker allocation data block information from the EDID.

Translate the EDID speaker allocation to audio infoframe
speaker allocation (different bit mapping) given the number
of channels of audio being played.

Set channel count information in HDMI_FC_AUDICONF0.
Set speaker allocation information in HDMI_FC_AUDICONF2.

From CEA-861-D spec:
NOTE—HDMI requires the CT, SS and SF fields to be set to 0 (Refer
to Stream Header) as these items are carried in the audio stream.

Signed-off-by: Alan Tull <r80115@freescale.com>
11 years agoENGR00180350-1 HDMI set infoframe information
Alan Tull [Wed, 18 Apr 2012 16:40:08 +0000 (11:40 -0500)]
ENGR00180350-1 HDMI set infoframe information

Get speaker allocation data block information from the EDID.

Translate the EDID speaker allocation to audio infoframe
speaker allocation (different bit mapping) given the number
of channels of audio being played.

Set channel count information in HDMI_FC_AUDICONF0.
Set speaker allocation information in HDMI_FC_AUDICONF2.

From CEA-861-D spec:
NOTE—HDMI requires the CT, SS and SF fields to be set to 0 (Refer
to Stream Header) as these items are carried in the audio stream.

Signed-off-by: Alan Tull <r80115@freescale.com>
11 years agoENGR00180636: tty/imx: lock check while handle sysrq message
Jason Liu [Wed, 11 Apr 2012 05:21:15 +0000 (13:21 +0800)]
ENGR00180636: tty/imx: lock check while handle sysrq message

Since the port->lock has already been hold when enter rx_interrupt,
and thus hold it on during handle_sysrq. We need check whether the
current console_write is for the sysrq message output or not and use
the correct lock mechanism.

Signed-off-by: Jason Liu <r64343@freescale.com>
11 years agoENGR00180624 Merge vivante 4.6.7p1 kernel part code
Loren Huang [Tue, 24 Apr 2012 04:21:24 +0000 (12:21 +0800)]
ENGR00180624 Merge vivante 4.6.7p1 kernel part code

Merge vivante 4.6.7p1 kernel part code

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
11 years agoENGR00180640 camera: enable dual camera configuration in menuconfig
Yuxi Sun [Tue, 24 Apr 2012 06:56:21 +0000 (14:56 +0800)]
ENGR00180640 camera: enable dual camera configuration in menuconfig

enable dual camera configuration in menuconfig, and set ov5642 as
the first registered camera

Signed-off-by: Yuxi Sun <b36102@freescale.com>
11 years agoENGR00180618 VDOA: Add vdoa_iram cmdline options and reduce used IRAM size
Wayne Zou [Tue, 24 Apr 2012 00:28:05 +0000 (08:28 +0800)]
ENGR00180618 VDOA: Add vdoa_iram cmdline options and reduce used IRAM size

Add vdoa_iram command line options and reduce used IRAM size
by default to 72KBytes. So by default it only support
partially interleaved 4:2:0 output format.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00179636-03 - i.MX6 : Enable ethernet NAPI method in default.
Fugang Duan [Fri, 20 Apr 2012 10:27:50 +0000 (18:27 +0800)]
ENGR00179636-03 - i.MX6 : Enable ethernet NAPI method in default.

- Enable ethernet NAPI method in default, which can reduce cpu
  loading and RX FIFO overruns in busy system.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00179636-02 - FEC : Enet RX FIFO overruns issue.
Fugang Duan [Fri, 20 Apr 2012 10:16:24 +0000 (18:16 +0800)]
ENGR00179636-02 - FEC : Enet RX FIFO overruns issue.

- Increase RX BD size to 384 entrys from 16 entrys, which
  can reduce the overruns number in busy system.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00179636-01 - FEC : Enet RX FIFO overruns issue.
Fugang Duan [Fri, 13 Apr 2012 08:57:10 +0000 (16:57 +0800)]
ENGR00179636-01 - FEC : Enet RX FIFO overruns issue.

- Add NAPI methods.
  NAPI can improve the performance of high-speed networking,
  which can reduce the cpu loading of interrupt generate and
  drop packets.
- Enet RX FIFO overruns number has been reduced by NAPI method.

Signed-off-by: Fugang Duan <B38611@freescale.com>
11 years agoENGR00180537 [MX6]Fix standby unstable issue
Anson Huang [Mon, 23 Apr 2012 08:50:54 +0000 (16:50 +0800)]
ENGR00180537 [MX6]Fix standby unstable issue

For the standby mode, we force SOC enter STOP mode
and drop the VDDARM_IN and VDDSOC_IN to 0.9V, we need
to disable L1 and L2 cache and invalidate L1 cache when
system resume, as the L1 cache memory's power is dropped
during standby, need to do the invalidation before re-enable
it.

Signed-off-by: Anson Huang <b20788@freescale.com>
11 years agoENGR00180297 WM8962: stereo record on AMIC
Gary Zhang [Mon, 23 Apr 2012 06:53:38 +0000 (14:53 +0800)]
ENGR00180297 WM8962: stereo record on AMIC

Implement stereo recording feature on analog mic

Signed-off-by: Gary Zhang <b13634@freescale.com>
11 years agoENGR00179722: MLB: set correct mlb sys clock in mx6dl
Terry Lv [Mon, 16 Apr 2012 09:44:12 +0000 (17:44 +0800)]
ENGR00179722: MLB: set correct mlb sys clock in mx6dl

In Rigel validatioin, the MLB sys_clock isn't using the right frequency
after boot.
In arik, the register CBCMR controls gpu2d clock, not mlb clock, mlb is
sourced from axi_clock.
But In rigel, the axi clock is lower than in mx6q, so mlb need to find a
new clock root. The gpu2d clock is then root of mlb clock in rigel.
Thus we need to add setting to support this change.

Signed-off-by: Terry Lv <r65388@freescale.com>
11 years agoENGR00171077 ESAI: Ends of record should not impact playback
Lionel Xu [Fri, 20 Apr 2012 11:33:33 +0000 (19:33 +0800)]
ENGR00171077 ESAI: Ends of record should not impact playback

The mute process in shutdown function should only be limited to playback, or
it will influence each other when they running together.

Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
11 years agoENGR00180412 MX6 SATA: Enable PHY in the SATA initilization
Richard Zhu [Fri, 20 Apr 2012 06:37:56 +0000 (14:37 +0800)]
ENGR00180412 MX6 SATA: Enable PHY in the SATA initilization

iENGR00179574: MX6- Add bus frequency scaling support disable
SATA PHY defaultly
Enable PHY in the SATA initilization, make sure the SATA work well.

Signed-off-by: Richard Zhu <r65037@freescale.com>
11 years agoENGR00180229-2 VDOA: disable vdoa clock when no used
Wayne Zou [Wed, 18 Apr 2012 08:45:48 +0000 (16:45 +0800)]
ENGR00180229-2 VDOA: disable vdoa clock when no used

Disable vdoa clock when no used

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00180229-1 V4L2: Fix a bug when doing tiled format deinterlaced
Wayne Zou [Wed, 18 Apr 2012 08:30:28 +0000 (16:30 +0800)]
ENGR00180229-1 V4L2: Fix a bug when doing tiled format deinterlaced

Initialize paddr_n when doing vdoa+vdi deinterlaced,
when doing tiled format deinterlaced.

Signed-off-by: Wayne Zou <b36644@freescale.com>
11 years agoENGR00180231 mx6q arm2 ONFI NAND clock change
Allen Xu [Thu, 19 Apr 2012 06:26:16 +0000 (14:26 +0800)]
ENGR00180231 mx6q arm2 ONFI NAND clock change

change clock source to enfc clock on mx6q arm2 lpddr board for ONFI nand
when enable ddr mode

Signed-off-by: Allen Xu <allen.xu@freescale.com>
11 years agoENGR00172292 usb otg: enable dtds postpone free on mx6
Xinyu Chen [Thu, 19 Apr 2012 09:04:57 +0000 (17:04 +0800)]
ENGR00172292 usb otg: enable dtds postpone free on mx6

We found this bug occurs again on mx6 when running
CTS with ADB over USB. The system will hang without
any log, and screen a little mess.
It's proved to be a known USB IP issue: USB controller
may access a wrong address for the dTD and then hang.
Re enable this workaround to avoid any system unstability.

Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
11 years agoENGR00180055 Steer configuration to enable AUD5_RXD signal
Alejandro Sierra [Tue, 17 Apr 2012 19:40:48 +0000 (14:40 -0500)]
ENGR00180055 Steer configuration to enable AUD5_RXD signal

Steer configuration to enable AUD5_RXD signal

Signed-off-by: Alejandro Sierra <b18039@freescale.com>
11 years agoENGR00180230 MX6 PCIE: enlarge the eye diagram and force to GEN1
Richard Zhu [Tue, 17 Apr 2012 02:24:50 +0000 (10:24 +0800)]
ENGR00180230 MX6 PCIE: enlarge the eye diagram and force to GEN1

* Adjust the parameters, enlarge the eye diagram.
* Force to the PCIE GEN1 speed.

Signed-off-by: Richard Zhu <r65037@freescale.com>
11 years agoENGR00180096 change NAND clock source to pll2_pfd_400M
Allen Xu [Wed, 18 Apr 2012 02:15:27 +0000 (10:15 +0800)]
ENGR00180096 change NAND clock source to pll2_pfd_400M

change clock source explicitly by calling set_parent() function

Signed-off-by: Allen Xu <allen.xu@freescale.com>