make shi [Thu, 18 Oct 2012 07:59:18 +0000 (15:59 +0800)]
ENGR00230167 MX6 regulator: enable and raise the voltage of USB 3p0 LDO
The USB FS eye test will fail in MX6 board if the 3V USB phy LDO is not enabled.
Setting enable bit (bit-0) of LDO 3p0 will make 3p0 LDO to use bandgap output as
reference voltage, LDO output will be accurate. And HW team suggest that it is
better to raise the voltage of USB 3p0 phy LDO 3.2V to pass the USB compliance
testing.
- Implement vdd3p0 regulator enable and disable function to support
enable and disable the LDO 3p0 regulator.
- Use regulator API to enable the USB 3p0 phy LDO and raise the LDO
to 3.2V during system boot up. And disable the LDO before system
enter suspend and enable the LDO again after system resume.
Wayne Zou [Wed, 24 Oct 2012 01:36:00 +0000 (09:36 +0800)]
ENGR00230910 IPU: wrong display to downsize large resolution frame on split mode
Fix bug: IPU IC resize ratio overflow when downsizing large resolution frame
using split mode, for example downsize 4080x2720 frame into 1920x1080 frame.
Otherwise, the downsized frame is wrong.
Chen Liangjun [Wed, 24 Oct 2012 04:31:59 +0000 (12:31 +0800)]
ENGR00230920-1 HDMI AUDIO: add support for HDMI audio module build
HDMI driver can be divided into 3 parts: machine driver, platform
driver, codec driver.To support HDMI AUDIO loadable module build, HDMI
machine driver should be built as loadable.
In this patch, adjust HDMI audio driver's struct: move HDMI audio platform
driver to snd-soc-imx-objs(snd-soc-imx-objs would always be
build-in).In this case, user need only build HDMI AUDIO machine driver
as loadable.
Robby Cai [Mon, 15 Oct 2012 13:36:44 +0000 (21:36 +0800)]
ENGR00229665 pxp: correct crop setting
The settings in the PXP_PS_BUF, PXP_OUT_PS_ULC, and PXP_OUT_PS_LRC will
determine the subset of the PS buffer, or clipped PS source buffer, that
will be used in the output buffer.
HW_PXP_OUT_PS_LRC should set the scaled output size rather than the origin
size when scaling.
Please refer to the "Clipping source images" section in RM for how it works.
Michael Minnick [Tue, 16 Oct 2012 23:07:20 +0000 (18:07 -0500)]
ENGR00227965 EPDC: Init sequence leaves EDPC clocks on
A small logic bug prevents the init sequence from properly turning
off the clocks. This leads to the clocks being always on
if the first update does not complete due to the screen being blanked.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Robby Cai [Thu, 11 Oct 2012 09:18:15 +0000 (17:18 +0800)]
ENGR00227890 ts: fix elan touch screen gets no response upon suspend/resume
To reproduce:
1. let system enter suspend mode
2. touch the screen
3. after the system resumes, touch screen does not respond again.
The cause:
The touch screen interrupt is triggered by falling edge. During suspend stage,
once the screen has ever been touched, then the interrupt line will be always
pulled low. Since elan ts chip is always powered on and the interrupt gets no
chance to be handled during suspend stage, the interrupt line can not recover
to high to detect a new one.
Workaround:
Read out the pending data to make the touch screen come back alive.
Signed-off-by: LiGang <b41990@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com>
Alejandro Sierra [Mon, 15 Oct 2012 23:13:47 +0000 (18:13 -0500)]
ENGR00229725 Sabreauto: Support NAND SPINOR NOR SD on same config
Configuration file modified to support NAND flash, SPI-NOR,
WEIM NOR and SD card on the same image.
Bootloader arguments will be used to choose between them.
Arguments on uboot are:
spi-nor
weim-nor
By default NAND is configured if neither spi-nor or weim-nor are used
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
Nicolin Chen [Tue, 16 Oct 2012 08:20:03 +0000 (16:20 +0800)]
ENGR00225520 SDMA:fix kernel dump occasionally during I2C stress test
Stress test with I2C devices occasionally caused kernel dump and panic:
==========================dump=start==========================
v4l_capture_testapp 0 TINFO :
Color space conversion YUV420->RGB565X success!
v4l_capture_testapp 0 TINFO :
Color space conversion YUV420->RGB565X success!
clean up environment...VPU interrupt received.
Unable to handle kernel paging request at virtual address ffdf401a
pgd = ba2a4000
[ffdf401a] *pgd=4fe1a811, *pte=00000000, *ppte=00000000
Internal error: Oops: 7 [#1] PREEMPT SMP
Modules linked in: mxc_v4l2_capture ipu_still ipu_bg_overlay_sdc
ipu_prp_enc ipu_fg_overlay_sdc ipu_csi_enc ov5642_camera
camera_sensor_clock [last unloaded: ipu_csi_enc]
CPU: 0 Not tainted (3.0.35-2039-g267e004 #1)
PC is at sdma_int_handler+0x144/0x1a4
LR is at sdma_int_handler+0x70/0x1a4
pc : [<802663f4>] lr : [<80266320>] psr: 60000193
sp : ba3e7ca8 ip : bfee2100 fp : 00000001
r10: 80a67200 r9 : 80acbcf0 r8 : 00000003
r7 : 00000001 r6 : 00000001 r5 : 00000002 r4 : bfee20e0
r3 : ffdf4000 r2 : 00010104 r1 : ffdf4018 r0 : bfee2104
Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c53c7d Table: 4a2a404a DAC: 00000015
Process mxc_vpu_test.ou (pid: 3277, stack limit = 0xba3e62f0)
Stack: (0xba3e7ca8 to 0xba3e8000)
7ca0: 80038f40bfee2000002977e3bf9cda80 80a6724c00000000
7cc0: 000000000000002280acbcf080a6720000000001800a5cb8 0000f08f00000000
[<802663f4>] (sdma_int_handler+0x144/0x1a4)
from [<800a5cb8>] (handle_irq_event_percpu+0x50/0x180)
[<800a5cb8>] (handle_irq_event_percpu+0x50/0x180)
from [<800a5e24>] (handle_irq_event+0x3c/0x5c)
[<800a5e24>] (handle_irq_event+0x3c/0x5c)
from [<800a81a8>] (handle_fasteoi_irq+0xbc/0x154)
[<800a81a8>] (handle_fasteoi_irq+0xbc/0x154)
from [<800a5620>] (generic_handle_irq+0x28/0x3c)
[<800a5620>] (generic_handle_irq+0x28/0x3c)
from [<80040830>] (handle_IRQ+0x4c/0xac)
[<80040830>] (handle_IRQ+0x4c/0xac)
from [<8003f9cc>] (__irq_svc+0x4c/0xe8)
[<8003f9cc>] (__irq_svc+0x4c/0xe8)
from [<800764f4>] (__do_softirq+0x4c/0x140)
[<800764f4>] (__do_softirq+0x4c/0x140)
from [<80076a90>] (irq_exit+0x94/0x9c)
[<80076a90>] (irq_exit+0x94/0x9c)
from [<8003a1b4>] (do_local_timer+0x70/0x90)
[<8003a1b4>] (do_local_timer+0x70/0x90)
from [<8003f9cc>] (__irq_svc+0x4c/0xe8)
Exception stack(0xba3e7de8 to 0xba3e7e30)
[<8003f9cc>] (__irq_svc+0x4c/0xe8)
from [<80071a88>] (vprintk+0x328/0x4a8)
[<80071a88>] (vprintk+0x328/0x4a8)
from [<804ddb28>] (printk+0x1c/0x2c)
[<804ddb28>] (printk+0x1c/0x2c)
from [<80390de0>] (vpu_ioctl+0x2cc/0x864)
[<80390de0>] (vpu_ioctl+0x2cc/0x864)
from [<800fc314>] (do_vfs_ioctl+0x80/0x54c)
[<800fc314>] (do_vfs_ioctl+0x80/0x54c)
from [<800fc818>] (sys_ioctl+0x38/0x5c)
[<800fc818>] (sys_ioctl+0x38/0x5c)
from [<8003ff80>] (ret_fast_syscall+0x0/0x30)
Code: e594101ce5943038e0811081e0831101 (e5d13002)
---[ end trace 82daf36a5a07d470 ]---
Kernel panic - not syncing: Fatal exception in interrupt
Rebooting in 60 seconds..
==========================dump=end==========================
This kernel dump only happened after one period of stress-test's done.
From the dump info above, we just located the issue happened in SDMA driver.
Regularly, it'd not be any problem when sdma_int_handler()'s called. But after
tracing, we found that in those occasional times, the last one irq of a channel
hadn't been responded while sdma_free_chan_resources() was already done.
sdma_free_chan_resources() should be called in the end of the procedure. Any
irq wouldn't occur after its resources're freed.
But considering about stress test, the test scripts uses "kill" cmd to close
aplay, which means pcm_free() might be called before last buffer's transmission
was finished. Plus, many modules're working in the same time during the test.
So CPU0, the only core can handle irq, would be busy with irq-handlings, while
the other CPU cores(i.e. CPU1~3) might be idle and deal with free() much faster
than CPU0's irq-handling. Then kernel panic.
Since we know, in some extreme circumstances, the irq would not be handled in
time, we can manually handle the irq ONLY IF we could still detect one irq to
the channel in the beginning of free(), right before its resources's gonna be
freed.
This Patch added checking code in the beginning of sdma_free_chan_resources()
to detect when the channel's gonna be freed if there's still one irq pended.
If so, just handle the irq manually before we free it.
Again, considering about sdma_int_handler() might be running at the same time,
and if it already cleared the value of reg but hadn't handled the irq yet, also
added code to pend free() until irq to the channel was handled.
Sheng Nan [Wed, 17 Oct 2012 06:55:10 +0000 (14:55 +0800)]
ENGR00229962 Capture: ov5642/ov5640: update sensor params even if s_parm failed
ioctl_s_parm for ov5642 and ov5640, it didn't check if sensor changed mode
successfully.
So it updates the sensor parameters with new framerate and new mode even
if the sensor failed to change mode.
The original framerate and mode is useful for the exposure calculation.
It should keep consistent with sensor actual work mode.
- This patch checks the return value of function which changes sensor mode
If it succeed, update sensor parameters.
ENGR00229695 MX6x-Set RBC counters correctly in STOP mode.
The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.
With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
Sheng Nan [Mon, 15 Oct 2012 09:49:27 +0000 (17:49 +0800)]
ENGR00224964-1 Capture: ov5642: 5M mode works at low frame rate
current setting of 5M (QSXGA) mode, sensor works at 2.5fps.
the expected frame rate is 7.5fps.
- use new ov5642 QSXGA firmware get from ov
change sensor PLL settings 0x3010/0x3012
QSXGA frame rate changes from 2.5 -- 7.5fps
- change mode between QSXGA@15fps and VGA@15fps go through quick change path.
modify QSXGA_VGA quick change firmware due to the QSXGA PLL setting changes.
keep value of 0x3010/0x3012 the same as VGA@15fps original value.
Anson Huang [Mon, 15 Oct 2012 23:01:17 +0000 (19:01 -0400)]
ENGR00229630 vpu: need to manage pu regulator in suspend/resume
If VPU is working before suspend, we need to disable its regulator
to make sure regulator can be off before suspend, then enable
its regulator before resume to work, we check vpu's open_count
to determine whether to disable/enable its regulator.
Michael Minnick [Fri, 12 Oct 2012 18:52:36 +0000 (13:52 -0500)]
ENGR00229291 EPDC: MX6: Treat fully-collided VOID update as a collision
The EPDC set the UPD_VOID (i.e. cancelled) bit in two cases:
1. No pixels needed updating
2. All pixels collided (COL bit also set)
The driver was miss-handling case 2. This fix causes case 2
to be treated as a collision and the update to be resubmitted.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
ENGR00229441 MX6SL-Reset MMDC read FIFO in low power IDLE
MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.
Jack Lee [Wed, 3 Oct 2012 05:31:47 +0000 (13:31 +0800)]
ENGR00223348 EPDC: Unable to enable DISPLAY regulator
In the maxim 17135 driver, the power good is confirmed by the
power good GPIO polarity change when comparing the status at
the beginning of driver probe and display regulator enabled.
However, it is not reliable since the initial value of the GPIO
is not constant. Normally, it is 1 but it can be 0 after system reset
unexpectedly. Now, it is changed to POK bit checking in FAULT register.
ENGR00229470-2 MX6SL-Add support for debug UART to be sourced from 24MHz.
If "debug_uart" is specified in the command line, uart will
be sourced from 24MHz XTAL. This is required for getting the
correct power measurements on MX6SL.
Certain analog power optimizations are done only if ALL PLLs
are bypassed on MX6SL. To verify this path, we need to ensure
that UART is not sourced from PLL3.
ENGR00229470-1 MX6SL-Add support for debug UART to be sourced from 24MHz.
If "debug_uart" is specified in the command line, uart will
be sourced from 24MHz XTAL. This is required for getting the
correct power measurements on MX6SL.
Certain analog power optimizations are done only if ALL PLLs
are bypassed on MX6SL. To verify this path, we need to ensure
that UART is not sourced from PLL3.
Sheng Nan [Sat, 13 Oct 2012 06:33:13 +0000 (14:33 +0800)]
ENGR00211376 Capture: ov5640_mipi: the QVGA is brighter
change ov5640_init_mode sequence according to ov's suggestion
ov5640 support two method of size switching, scaling and subsampling
exposure calculation when change size between scaling and subsampling
- scaling: image size bigger than 1280*960
- subsampling: image size smaller than 1280*960
This patch changes the sequence of ov5640_init_mode()
1. setting mipi csi2 (no change).
2. check mode
- if it is in INIT_MODE, go throught initial procedure
- if sensor changes between scaling and subsampling,
go through exposure calcualtion
- otherwise, configure mode directly.
3. other procedures keep the same.
ENGR00229464 MX6SL-Update the SOC voltages based on datasheet
Update the VDDARM and VDDSOC voltages based on IMX6SLCEC_Rev0
datasheet.
As the voltages for ARM @ 198MHz and ARM @ 396MHz are the same
remove the 198MHz working point.
Michael Minnick [Tue, 9 Oct 2012 23:06:31 +0000 (18:06 -0500)]
ENGR00229290 EPDC: MX6: Adjust number of LUTs for 5-bit waveform
When a 5-bit waveform is loaded, the maximum number of available
LUTs is 16. The LUT allocator must account for this.
Note that 5-bit waveform loading is currently not supported in the
driver. However, this fix makes sure the LUT allocator is correct
when 5-bit support is added.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Ryan QIAN [Mon, 8 Oct 2012 23:44:34 +0000 (07:44 +0800)]
ENGR00227420 mmc: sdhci: shorten the delay on disabling clk
- change the delay from 10 * HZ to 1 * HZ, though (1 * HZ) might not be the
best, just as a base.
1. Since the request has been moved out of interrupt context, there will be no
more calling enable_clk in interrupt context. So it's not necessary to keep
such a long delay on disabling clock in order to save power.
2. Still keeping the 1*HZ of delay is to avoid frequently enabling/disabling
clock.
make shi [Fri, 12 Oct 2012 09:01:33 +0000 (17:01 +0800)]
ENGR00229354 Mx6 USB device: fix wrong handle for invalid USB_FEATURE requests
There is a bug udc driver handle invalid USB_FEATURE requests in current bsp.
The invalid USB_FEATURE request will be handled as a valid USB_FEATURE request.
We should set protocol stall on ep0 to handle invalid USB_FEATURE requests.
Terry Lv [Fri, 12 Oct 2012 06:39:34 +0000 (14:39 +0800)]
ENGR00229327: otp: driver causes warning when enable CONFIG_LOCKDEP
When CONFIG_LOCKDEP is enabled, it will cause warings:
------------[ cut here ]------------
WARNING: at kernel/lockdep.c:2885 sysfs_add_file_mode+0x54/0xc0()
Modules linked in:
[<80046364>] (unwind_backtrace+0x0/0xfc) from [<800758c0>]
(warn_slowpath_common+0x4c/0x64)
[<800758c0>] (warn_slowpath_common+0x4c/0x64) from [<800758f4>]
(warn_slowpath_null+0x1c/0x24)
[<800758f4>] (warn_slowpath_null+0x1c/0x24) from [<801536c4>]
(sysfs_add_file_mode+0x54/0xc0)
[<801536c4>] (sysfs_add_file_mode+0x54/0xc0) from [<8015616c>]
(internal_create_group+0xdc/0x1d8)
[<8015616c>] (internal_create_group+0xdc/0x1d8) from [<80524110>]
(fsl_otp_probe+0x168/0x1d4)
[<80524110>] (fsl_otp_probe+0x168/0x1d4) from [<802b42e8>]
(platform_drv_probe+0x18/0x1c)
[<802b42e8>] (platform_drv_probe+0x18/0x1c) from [<802b2fe4>]
(driver_probe_device+0x98/0x1a4)
[<802b2fe4>] (driver_probe_device+0x98/0x1a4) from [<802b3184>]
(__driver_attach+0x94/0x98)
[<802b3184>] (__driver_attach+0x94/0x98) from [<802b280c>]
(bus_for_each_dev+0x60/0x8c)
[<802b280c>] (bus_for_each_dev+0x60/0x8c) from [<802b2180>]
(bus_add_driver+0x190/0x268)
[<802b2180>] (bus_add_driver+0x190/0x268) from [<802b3788>]
(driver_register+0x78/0x13c)
[<802b3788>] (driver_register+0x78/0x13c) from [<800394ac>]
(do_one_initcall+0x30/0x170)
[<800394ac>] (do_one_initcall+0x30/0x170) from [<800083cc>]
(kernel_init+0x98/0x144)
[<800083cc>] (kernel_init+0x98/0x144) from [<8004003c>]
(kernel_thread_exit+0x0/0x8)
---[ end trace 877415a10b5d9cb1 ]---
also, on imx6sl, it will cause below issue:
BUG: key bffea2e4 not in .data!
BUG: key bffea300 not in .data!
BUG: key bffea31c not in .data!
BUG: key bffea338 not in .data!
BUG: key bffea354 not in .data!
BUG: key bffea370 not in .data!
BUG: key bffea38c not in .data!
BUG: key bffea3a8 not in .data!
BUG: key bffea3c4 not in .data!
BUG: key bffea3e0 not in .data!
BUG: key bffea3fc not in .data!
BUG: key bffea418 not in .data!
BUG: key bffea434 not in .data!
BUG: key bffea450 not in .data!
BUG: key bffea46c not in .data!
BUG: key bffea488 not in .data!
BUG: key bffea4a4 not in .data!
BUG: key bffea4c0 not in .data!
BUG: key bffea4dc not in .data!
We need to call sysfs_attr_init to initlize sysfs attr.
Huang Shijie [Thu, 11 Oct 2012 01:50:13 +0000 (09:50 +0800)]
ENGR00227835 imx6q: gpmi: fix the warning when no NAND chip exits
If there is no nand chip in the board, the kernel will prints out the
following warning message:
------------[ cut here ]------------
WARNING: at arch/arm/plat-mxc/clock.c:63 clk_disable+0x48/0x90()
clock enable/disable mismatch! clk apbh_dma_clk
Modules linked in:
[<80044f48>] (unwind_backtrace+0x0/0xfc) from
[<80070ac0>] (warn_slowpath_common+0x4c/0x64)
[<80070ac0>] (warn_slowpath_common+0x4c/0x64) from
[<80070b6c>] (warn_slowpath_fmt+0x30/0x40)
[<80070b6c>] (warn_slowpath_fmt+0x30/0x40) from
[<8005ee60>] (clk_disable+0x48/0x90)
[<8005ee60>] (clk_disable+0x48/0x90) from
[<80255e48>] (dma_chan_put+0x4c/0x50)
[<80255e48>] (dma_chan_put+0x4c/0x50) from
[<80255f18>] (dma_release_channel+0x24/0x94)
[<80255f18>] (dma_release_channel+0x24/0x94) from
[<802ad8ec>] (release_resources+0x58/0x6c)
[<802ad8ec>] (release_resources+0x58/0x6c) from
[<80445964>] (gpmi_nand_probe+0x44c/0x4ec)
[<80445964>] (gpmi_nand_probe+0x44c/0x4ec) from
[<80281868>] (platform_drv_probe+0x18/0x1c)
[<80281868>] (platform_drv_probe+0x18/0x1c) from
[<80280590>] (driver_probe_device+0x98/0x1a4)
[<80280590>] (driver_probe_device+0x98/0x1a4) from
[<80280728>] (__driver_attach+0x8c/0x90)
[<80280728>] (__driver_attach+0x8c/0x90) from
[<8027fdd0>] (bus_for_each_dev+0x60/0x8c)
[<8027fdd0>] (bus_for_each_dev+0x60/0x8c) from
[<8027f75c>] (bus_add_driver+0x184/0x25c)
[<8027f75c>] (bus_add_driver+0x184/0x25c) from
[<80280d1c>] (driver_register+0x78/0x13c)
[<80280d1c>] (driver_register+0x78/0x13c) from
[<80022d80>] (gpmi_nand_init+0xc/0x3c)
[<80022d80>] (gpmi_nand_init+0xc/0x3c) from
[<80039478>] (do_one_initcall+0x30/0x16c)
[<80039478>] (do_one_initcall+0x30/0x16c) from
[<80008410>] (kernel_init+0x98/0x144)
[<80008410>] (kernel_init+0x98/0x144) from
[<8003ffb4>] (kernel_thread_exit+0x0/0x8)
---[ end trace c28d32057fe33a29 ]---
This mxs_dma_clk's usecount is not correctly changed which causes the kernel
shows this warning.
This patch adds proper clk_disable_unprepare/clk_prepare_enable in
the mxs-dma driver to balance the mxs_dma_clk's usecount.
Also put the mxs_dma_clk when the gpmi exits.
Liu Ying [Wed, 10 Oct 2012 07:13:30 +0000 (15:13 +0800)]
ENGR00227681 IPUv3:Use spinlock to protect buf ready reg
There are several channels' buffer ready bits controlled
by a single 32bit register-IPU_CHA_BUFx_RDY. These buffer
ready can be write-one-to-set or write-one-to-clear, which
is controlled by IPU_GPR register. v4l2 capture driver will
touch the buffer ready registers in interrupt context, so,
currently, ipu->mutex_lock is bypassed with the context.
Then, a race condition is that v4l2 capture driver interrupt
context tries to set a channel buffer ready, while, another
context tries to disable another channel(clear buffer ready
bit), which may cause v4l2 capture driver fails to set buffer
ready(SMFC0_FRM_LOST error may happen). This patch uses ipu->
rdy_reg_spin_lock to protect buffer ready registers to fix
the race condition issue and rename ipu->spin_lock to ipu->
int_reg_spin_lock.
1) We get busy_lock semaphore before we get a dqueue event, so, when user
is blocked at DQBUF ioctrl, the user will also be blocked at QBUF ioctrl,
then the video performance will drop. This patch changes to get busy_lock
semaphore to protect DQBUF ioctrl until we successfully get a dqueue event.
2) Use queue_int_lock and dqueue_int_lock spinlocks to protect working_q/
ready_q/done_q in the end of frame interrupt handler camera_callback(), in
case, the handler and VIDIOC_QBUF/VIDIOC_DQBUF ioctrls are called on diff-
erent cores at the same time.
3) Protect ready_q with queue_int_lock spinlock in mxc_streamon(), in case,
VIDIOC_STREAMON and VIDIOC_QBUF ioctrls are called on different cores at
the same time.
1) Change to enable/disable mclk only in open, release,
suspend and resume functions, since we may simply think that
sensor or mclk will be used soon after cam->open_count is non-zero.
2) Fix a bug when calling ipu_csi_enable_mclk_if() with wrong
parameter(cam->csi should be cam->mclk_source) in mxc_v4l2_close()
and in mxc_v4l2_s_ctrl() with V4L2_CID_MXC_SWITCH_CAM control id.
Robby Cai [Tue, 9 Oct 2012 11:59:25 +0000 (19:59 +0800)]
ENGR00227568 elcdif: fix fb wait for vsync timeout when suspend and resume
When suspend, the lcdif and panel will be stopped. When resume, fb_set_par()
will be called, in which the lcdif and the panel will be re-initialized.
However, fb_set_par() also checks the parameters via mxc_elcdif_fb_par_equal(),
which will probably make fb_set_par() just return with them un-initialized.
And thus, the interrupt will not come. This patch added a varible to check
whether they're running along with mxc_elcdif_fb_par_equal() checking to
fix the issue. If not running, re-initialization will be forcely done.
Robby Cai [Tue, 9 Oct 2012 08:36:41 +0000 (16:36 +0800)]
ENGR00227502-1 csi/v4l2: Implement probe and remove function for csi v4l2 driver
Because csi_v4l2 driver will only be loaded when needed(by assign 'csi' in
kernel cmdline), we use standard driver framework to easily bind the device and
driver. Otherwise, we will meet the problem like the crash as below when do
suspend/resume due to the resource of csi not assigned at all if 'csi' not
passed in cmdline.
Anson Huang [Tue, 9 Oct 2012 19:30:20 +0000 (15:30 -0400)]
ENGR00227477 mx6qdl: system resume fail due to DDR not accessable
For DQ and DL, we must make sure DDR can be accessed after resume,
our code did NOT get a valid base address for MMDC to exit from
DVFS mode, need to fix it.
According to ARM, we only need to save r0-r3 and r12 before calling
C function.
Ryan QIAN [Mon, 8 Oct 2012 01:50:23 +0000 (09:50 +0800)]
ENGR00227241 mx6sl: clk: sdhc can not work at lp idle mode
issue:
Once entering low power idle mode, pll2_400 will be bypass which will change
the clk rate of sdhc root clk. so far, there's no mechanism to inform sdhc
for changing of root clk in current driver structure.
fix:
Revert "ENGR00226096 mx6sl: remove high set point for usdhc"
Ryan QIAN [Tue, 9 Oct 2012 00:58:41 +0000 (08:58 +0800)]
ENGR00220469 mmc: sdio: claim host on suspend and release on resuming
issue:
Since there's no sync mechanism between sdio bus suspending and sdio_irq_thread,
it will cause that sdio_irq_thread still makes sdhc request even after sdio bus
suspends.
fix:
On suspending sdio bus, claim host, so that:
1. mmc_sdio_suspend will wait for finishing of sdio_irq_thread.
2. sdio_irq_thread will be blocked even being scheduled.
And release host on resuming.
Acked-by: Aisheng DONG <b29396@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com>
Currently, the sequence and functionality we use to enter and exit
suspend causes us to hang upon resuming. It appears that this is being
caused by two things. The first is the powering off of the 2p5 rail
which powers the IO pullups and pulldowns. The DQS pins were
configured as pull downs. The second is switching the DQS pins from
differential to CMOS mode (and back). This second problem only
occurs on a few EVK boards.
It is believed that these changes are causing glitches on the mmdc DQS
pins which is putting garbage in the FIFO (or causing some other FIFO
problem). This patch adds two mmdc0 FIFO resets after exiting the
suspend. Two are thought to be needed per previous FIFO reset
experience by Mike Kjar.
Since the MMDC0 FIFO will be cleaned each time, we can now remove
the code that configured the DQS lines as pull downs as we no
longer care if they float.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
Robert Lee [Mon, 8 Oct 2012 21:15:27 +0000 (16:15 -0500)]
ENGR00227422: ARM: imx6sl: Adjust ARM and SOC stby voltages
According to the latest specification data, these rails should
go no lower than 900mV in standby mode. This patch modifies
the existing mx6sl board files and sets the pmic standby voltage
for these rails to be 925mV (extra 25mV to account for pmic accuracy).
Signed-off-by: Robert Lee <robert.lee@freescale.com>
ENGR00227426 MX6SL-Fix bugs in low power IDLE mode
Need to ensure that DDR IO pads are not floated when
a peripheral that needs DDR is active, for ex SDMA.
Also need to keep IPMUX clock enabled even when ARM
is in WFI, so set the CCGR bits accordingly.
Anson Huang [Tue, 9 Oct 2012 15:04:42 +0000 (11:04 -0400)]
ENGR00227425 mx6sl: Need to save all registers before calling C function
Different linker may use r12, we should save/restore all
registers(r0-r12) before calling C function to prevent
these registers from corruption in C code.
ENGR00227245 mx6q: Remove 400M setpoint for bus freq
Although 400M bus setpoint can save some SOC domain power,
but it will also bring some additional power consumption
to DDR3, and the DDR performace's drop could also lead to
more heat generated by COREs which will spent more time
waiting for DDR data ready, also, there is not many usecases
that need this setpoint, all in all, we should remove 400M
setpoint.
ENGR00227249 MX6SL-Add support for low latency STANDBY mode.
Change STANDBY mode to support the following for MX6SL:
1. assert VSTBY
2. ARM is power gated.
3. XTAL is ON
4. LDO 2P5 is disabled, weak 2P5 is enabled.
5. LDO 1p1 is enabled.
Implement this for a higher power but lower latency on resume
from STANDBY mode.
* Fix imx_dma_data duplicate struct definition
* Rename struct as name conflicts with imx_dma_data
struct defined at arch/arm/plat-mxc/include/mach/dma.h
* Update copyrigth year.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Michael Minnick [Wed, 26 Sep 2012 21:33:21 +0000 (16:33 -0500)]
ENGR00180348 EPDC: invalid data when width is 2048 or greater
This patch works around the 6DLS and 6SL chip errata:
ERR005313 EPDC: Incorrect data fetched when the buffer update width is
2048 pixels or greater
This patch breaks large updates into multiple updates, which works
around the problem on both 6DSL and 6SL. This patch does not use the
Group Update feature, which may improve things further on 6SL.
This patch does not include for support for any particular large panel.
It was tested on ED09705 (2400x1650). Support for ED09705 is
available in a separate patch.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
Robby Cai [Thu, 27 Sep 2012 15:50:08 +0000 (23:50 +0800)]
ENGR00225981-8 csi/imx6sl: add the platform-related setting
- add platform data for csi driver
- change the regulator name to reflect the voltage really used
- select OSC as csi parent clock to get 24MHz
- add an boot option to use csi feature while filter out the EPDC/SPDC, since
there are pin conflicts with xPDC.
- both ov5640 and ov5642 are verified okay, ov5640 is used by default.
- remove IPU from update_defconfig
ENGR00225960-02 FB: Support sii902x HDMI driver in ELCDIF FB
- Added mxcfb_elcdif_register_mode function.
- Create video mode list, and check default video mode
with video mode list before setting.
- Adjust elcdif pixel clock setting, reconfig elcdif pixel
parent clock video pll, get more accurate pixel clock
according video mode.
- Added video mode dump function for debug
Robin Gong [Tue, 25 Sep 2012 08:47:48 +0000 (16:47 +0800)]
ENGR00225735-3 GPU: add gpu regulator disable/enable in gpu driver
add gpu regulator management in gpu driver Signed-off-by: Robin Gong <b38343@freescale.com> Acked-by: Lily Zhang Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Tue, 25 Sep 2012 08:43:57 +0000 (16:43 +0800)]
ENGR00225735-2 VPU: add vpu regulator enable/disable in driver
add vpu regulator management including enable/disable in vpu driver. Mainly
in open/release and suspend/resume. Signed-off-by: Robin Gong <b38343@freescale.com>
Robin Gong [Tue, 25 Sep 2012 08:33:37 +0000 (16:33 +0800)]
ENGR00225735-1 PU anatop: PU regulator can be disabled/enabled by drivers
Before, PU regulator only be turned off in DSM, which means it kept on in
system normal mode even GPU/VPU driver didn't run. To decrease power number,
PU regulator can be disabled/enabled by GPU/VPU driver, and the voltage value
is tracked by VDDARM which change in cpufreq driver.The patch including:
1.implement PU regulator enable/disable interface in anatop regulator driver
2.remove gpu_power_down and gpu_power_up in system suspend/resume flow.
3.skip change pu regulator set if it has been disabled.
Note: There is three power supply on VDDPU:
a).Use internal anatop PU regulator, VDDDPU_IN is fixed. In this case,VDDPU_CAP
can be turned off or dynamic change by internal anatop(track with VDDSOCi_CAP).
In other words, it use "cpu_vddvpu" regulator as PU regulator,not only in GPU/
VPU driver, but also in cpufreq driver.Sabresd,Sololite EVK is in this case if
disable CONFIG_MX6_INTER_LDO_BYPASS.
b).Use external pmic regulator as PU regulator, it means in LDO bypass way
(CONFIG_MX6_INTER_LDO_BYPASS).But VDDPU_IN is connected with VDDSOC_IN. Because
VDDSOC can't be turned off for ever, and VDDPU track with VDDSOC always, we
remove "pu_id", so that cpufreq driver will never touch it.But GPU/VPU driver
will turn off/on VDDPU_CAP by disabling/enabling "cpu_vddvpu".In this case,
although VDDPU_IN is supplied by external pmic in hardware level, but we can't
turn off external pmic directly, because it connect with VDDSOC_IN.So only we
can do is turn off VDDPU_CAP by internal anatop regulator("cpu_vddvpu").Sabresd
,Sololite EVK is in this case if enable CONFIG_MX6_INTER_LDO_BYPASS.
c).Use external pmic regulator as PU regulator, it means in LDO bypass way
(CONFIG_MX6_INTER_LDO_BYPASS). And VDDPU_IN is in dependent with VDDSOC_IN(
whether short in VDDPU_IN with VDDPU_CAP directly or not).In this case,the only
thing we need to do is that add the right external vddpu regulator name to
"pu_id" in their boad file, and nothing else.
Just like below (arch/arm/mach-mx6/board-mx6sl_evk.c):
static struct mxc_dvfs_platform_data mx6sl_evk_dvfscore_data = {
.reg_id = "VDDCORE",
.soc_id = "VDDSOC",
*******************************************************************
.pu_id = "what you used VDDPU_IN regulator name from external pmic"
*******************************************************************
.reg_id = "cpu_vddgp",
.soc_id = "cpu_vddsoc",
.pu_id = "cpu_vddvpu",
......
ENGR00225894 MX6SL-Improve system IDLE power numbers
Add the following power optimizations when all PLLs
are either disabled or in bypass:
1. Disable 2P5 in system IDLE mode and enable weak 2P5.
2. Set OSC bias current to -37.5% just before the WFI instruction
and set it back to 0% after WFI.
3. Enable the low power bandgap and power down the regular
bandgap.
ENGR00226080 Update GC2000/GC320 AXI bus cache attribute
This patch changed the GPU AXI bus cache attribute
to improve the performance of fillrate bound case.
Here is some test result: BEFORE:AFTER (larger better)
mm06 samruai fps: 117.74:137.64
mm06 proxycon fps: 117.90:135.00
Fillrate with 1 tex: 251.3M:331.1M
Fillrate with 2 tex: 402.6M:475.4M
Ryan QIAN [Thu, 27 Sep 2012 08:12:56 +0000 (16:12 +0800)]
ENGR00226096 mx6sl: remove high set point for usdhc
- Due to usdhc ADMA mode has issue working with low bus freq, in
driver usdhc has been configured to SDMA mode already. So it is
not necessary to keep high set point flag any more.
Signed-off-by: Ryan QIAN <b32804@freescale.com> Acked-by: Dong Aisheng <b29396@freescale.com> Acked-by: Robby CAI <r63905@freescale.com>
This patch adds CONFIG_MX6_CLK_FOR_BOOTUI_TRANS support. Setting
this Kconfig may keep enable IPU related clocks and PWM clocks
and avoid setting IPU related clocks' parents when initializing
clock tree so that bootloader splashimage can transition to
kernel smoothly.
As there is only one IPU embedded in MX6DL and two IPUs embedded
in MX6DQ. The max ipuv3 fb platform driver number is two for
MX6DL and four for MX6DQ.
Liu Ying [Wed, 12 Sep 2012 01:43:12 +0000 (09:43 +0800)]
ENGR00223797-6 MX6 SabreSD:Initialize late init for IPUv3 fb pdata
This patch initializes late init field to false for IPUv3 fb pdata,
so we don't support late init by default unless we change them to
true in other places specificly.
Liu Ying [Wed, 12 Sep 2012 01:36:12 +0000 (09:36 +0800)]
ENGR00223797-5 MX6 SabreSD:Initialize bypass reset for IPUv3 pdata
This patch initializes bypass reset field to false for IPUv3 pdata,
so we don't support bypass reset by default unless we change them
to true in other places specificly.
Liu Ying [Tue, 11 Sep 2012 10:10:11 +0000 (18:10 +0800)]
ENGR00223797-4 IPUv3 fb:Support framebuffer late init
This patch adds late init support in IPUv3 fb driver
to avoid IPUv3 fb being re-initialized during probe if
a platform supports smooth transition from bootloader
splashimage to system UI. The re-initialization will
be delayed to the first time the user triggers
mxcfb_set_par() and unblank the framebuffer.
The following items are done to support this:
1) Move global alpha and color key setting in probe
after framebuffer is registered(before registering
we enable IPU hsp clock), because the 2 APIs enable
and disable IPU hsp clock which may cause IPU stops
running in ipuv3 fb probe function.
2) Do not clear framebuffer content in probe function
if late init is set. This is to avoid bootloader
splashimage content is cleared.
3) If late init is set, do not re-initialize and
unblank framebuffer in probe function, but initialize
and enable ipu display channel instead to enable
the ipu hsp clock. Refer to the code comment for
detail.
4) Delay register IPU interrupts used by framebuffer
until IPU hsp clock is enabled by 3). As the APIs
to register IPU interrupts may enable and disable
IPU hsp clock as well.
projects / karo-tx-linux.git / log