Chen-Yu Tsai [Thu, 22 May 2014 15:20:55 +0000 (23:20 +0800)]
pinctrl: sunxi: fix pin numbers passed to register offset helpers
The pin numbers passed to sunxi_*_reg helpers to get the correct
registers should be the pin offset for the PIO block, not the
absolute number we use that is based on the alphanumeric labels
Allwinner uses.
This patch subtracts .pin_base from the pin number passed to these
functions, so the driver accesses the correct registers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Alexander Stein [Thu, 24 Apr 2014 17:55:39 +0000 (19:55 +0200)]
pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
With commit 80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip)
gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The
associated GPIO chip for the IRQ chip is overwritten each time, because
they share the same hard IRQ line.
Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on
PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will
not be cleared, retriggering the ISR.
Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip
and walk the list in the irq handler.
Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard [Thu, 22 May 2014 14:25:27 +0000 (16:25 +0200)]
pinctrl: sunxi: Fix multiple registration issue
When the support for the PRCM muxer on the A31 has been added, the global
static pinctl_desc definition has been left as is. Unfortunately, this
structure is used to register the pinctrl device, and prior to this
registration, we set the name and pins field.
Since this structure is shared across instances, that means that the latest
registered pinctrl device wins in setting the name, pins and pins numbers,
which is not really a good thing.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard [Thu, 22 May 2014 14:47:12 +0000 (16:47 +0200)]
pinctrl: sunxi: Fix recursive dependency
Fix the following configuration error:
drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected!
drivers/pinctrl/sunxi/Kconfig:3: symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10
drivers/pinctrl/sunxi/Kconfig:9: symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI
Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI
one.
We still need to keep PINCTRL_SUNXI at the moment in order to preserve
bisectability. Indeed, during that merge window, we also introduced the
MACH_SUN* symbols. Since it's going through different trees, we can't rely on
the fact that the options will be there, while ARCH_SUNXI still select
PINCTRL_SUNXI.
Antoine Tenart [Mon, 19 May 2014 17:36:32 +0000 (19:36 +0200)]
pinctrl: berlin: add the BG2CD pinctrl driver
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Tenart [Mon, 19 May 2014 17:36:31 +0000 (19:36 +0200)]
pinctrl: berlin: add the BG2 pinctrl driver
Add the pin-controller driver for the Berlin BG2 SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Tenart [Mon, 19 May 2014 17:36:30 +0000 (19:36 +0200)]
pinctrl: berlin: add the BG2Q pinctrl driver
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Tenart [Mon, 19 May 2014 17:36:29 +0000 (19:36 +0200)]
pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs
The Marvell Berlin boards have a group based pinmuxing mechanism. This
adds the core driver support. We actually do not need any information
about the pins here and only have the definition of the groups.
Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
to mode 0:
Group Modes Offset Base Offset LSB Bit Width
GSM12 3 sm_base 0x40 0x10 0x2
So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
to set (sm_base + 0x40 + 0x10) &= ff3fffff.
As pin control registers are part of either chip control or system
control registers, that deal with a bunch of other functions we rely
on a regmap instead of exclusively remapping any resources.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jin Yao [Thu, 15 May 2014 15:28:47 +0000 (18:28 +0300)]
pinctrl: baytrail: Register GPIO chip after chip->to_irq is set
If chip->to_irq is NULL ACPI GPIO helpers don't register GPIO event
handlers thus preventing any ACPI GPIO triggered events. Solve this by
calling gpiochip_add() after we have set up drivers chip->to_irq hook.
Signed-off-by: Jin Yao <yao.jin@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jin Yao [Thu, 15 May 2014 15:28:46 +0000 (18:28 +0300)]
pinctrl: baytrail: Add back Baytrail-T ACPI ID
Now that the x86 dynamic IRQ allocation problem has been resolved with
commmit 62a08ae2a576 (genirq: x86: Ensure that dynamic irq allocation does
not conflict), we can add back Baytrail-T ACPI ID to the pinctrl driver.
This makes the driver to work on Asus T100 where it is needed for several
things like ACPI GPIO events and SD card detection.
References: https://bugzilla.kernel.org/show_bug.cgi?id=68291 Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Jin Yao <yao.jin@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Laurent Pinchart [Tue, 13 May 2014 11:37:46 +0000 (13:37 +0200)]
pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatform
In the multiplatform kernel case the IRQs associated with the PFC GPIOs
are specified through DT. The pinmux_irq irq field is thus ignored by
the code, and doesn't need to be set.
This will allow removing the mach/irq.h include from pfc-*.c files that
was required for the irq_pin() macro used to initialize the irq field.
Maxime Ripard [Tue, 13 May 2014 15:23:17 +0000 (17:23 +0200)]
pinctrl: sunxi: Enable the pinctrl Kconfig options by default
Enable the freshly introduced Kconfig options whenever their matching
architecture is enabled.
Since the Kconfig symbols for these machines are going through a different
tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig.
It should be removed eventually.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Mon, 5 May 2014 11:59:51 +0000 (13:59 +0200)]
pinctrl: rockchip: base regmap supplied by a syscon
This allows the basic registers of the general register files to be supplied
by a syscon instead of being mapped locally.
The GRF registers contain a lot more than pinctrl functions like dma, usb-phy
and general soc control and status registers, intermixed with the iomux, pull
and drive-strength registers.
Heiko Stübner [Mon, 5 May 2014 11:59:09 +0000 (13:59 +0200)]
pinctrl: rockchip: let pmu registers be supplied by a syscon
Currently the pmu registers containing pin pull settings on the rk3188 are mapped
locally when bank0 is instantiated. Add an alternative that can resolve the pmu
from a syscon phandle.
Linus Walleij [Fri, 9 May 2014 06:47:16 +0000 (08:47 +0200)]
Merge tag 'sunxi-pinctrl-for-3.16' of https://github.com/mripard/linux into devel
Pinctrl cleanup and reworks for 3.16
This serie of patch:
- Moves the Allwinner pinctrl driver to a folder of its own
- removes the sunxi-pinctrl-pins header, and split the driver into a core
one, with all the logic, and smaller drivers, one for each SoC, that
declare the pins, and will provide to the core the set of pins.
- And does a few cleanups here and there.
Maxime Ripard [Sat, 26 Apr 2014 20:28:54 +0000 (22:28 +0200)]
pinctrl: sunxi: Move the reset handling functions out of the core
The way that reset is handled right now is that it is made optional for every
pinctrl driver, while actually, it isn't used at all for the main pin
controllers so far, and while it's mandatory for the A31's secondary pin
controller.
Move the reset functions out of the core and in the driver, where they can be
made mandatory.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A20 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be.
This is the final step toward retiring pinctrl-sunxi-pins.h that used to define
all the pins for all the Allwinner SoCs in a single header, that would have in
turn result in having these structures in the final binary as many times as the
header was included.
We can finally remove that header, and remove all the driver part of the
pinctrl-sunxi core.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A31 special pins driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A31 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A13 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A10s pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Sat, 26 Apr 2014 19:59:50 +0000 (21:59 +0200)]
pinctrl: sunxi: Switch to devm_ioremap_resource
The previous code was calling of_iomap, which doesn't do any resource
management, and doesn't call request_mem_region either. Use
devm_ioremap_resource that do both.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Thu, 24 Apr 2014 14:06:52 +0000 (16:06 +0200)]
pinctrl: sunxi: Replace hardcoded pin defines by a macro
We previously had an evergrowing (and exhaustive) list of the pins that could
be used on any Allwinner SoCs. These defines were then used by each pinctrl
driver to declare the list of functions for this pin. Since it's pretty much
all boilerplate, we can remove it just by a single macro.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:07 +0000 (23:26 +0200)]
pinctrl: mvebu: new driver for Orion platforms
This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants of Orion5x, which are the three ones supported by the old
style MPP code in arch/arm/mach-orion5x/.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In some cases it is nice to be able to simply control a gpio output
via the PIN_CONFIG_OUTPUT option without having a driver control it.
Thus add support for it to the rockchip pinctrl driver.
pinctrl: rockchip: return a complete config in pinconf_get
Till now pinconf_get only set the argument value into the config parameter
effectively removing the actual config param value. As other pinctrl drivers
do, it might be nicer to keep the config param intact.
Therefore construct a real pinconfig value from param and arg in pinconf_get
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is
not converting an irqchip to a bank but converts a gpiochip
to a bank so rename it sirfsoc_gpiochip_to_bank().
Acked-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tomasz Figa [Mon, 14 Apr 2014 01:45:47 +0000 (10:45 +0900)]
pinctrl: exynos: Add driver data for Exynos3250
This patch adds driver data (bank list and EINT layout) for Exynos3250
to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
ports. There are 23 general port groups.
Changes from v1:
- Add signed-off of sender
- Post only separated patch for pinctrl from following patchset(v1)
: https://lkml.org/lkml/2014/4/10/286
Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stephen Warren [Mon, 14 Apr 2014 21:33:42 +0000 (15:33 -0600)]
pinctrl: tegra: print better error messages
When an attempt is made to configure an unsupported option on a pin,
print the DT property name of that option, so it's easier to debug
what the problem is.
Stephen Warren [Mon, 14 Apr 2014 21:33:40 +0000 (15:33 -0600)]
pinctrl: tegra: remove fsafe from data tables
The fsafe value in the pingroup data tables is only used to implement
tegra_pinctrl_disable(). The only reason this function is called is when
dynamically switching between pinmux states, i.e. when disabling the old
state before programming the new state. It's simpler to have the new
target state define the expected value of each pin (and all current DTs
do that). This also gives more flexibility, since it allows individual
boards explicit control over the "inactive" mux function for each pin,
rather than requiring it to be an SoC-specific value. Assuming this, we
can get rid of the fsafe value from the driver completely, thus saving
some more space in the driver tables.
While re-writing the content of tegra124_pingroups[], fix the indentation
to use a TAB instead of spaces.
Stephen Warren [Tue, 15 Apr 2014 17:00:50 +0000 (11:00 -0600)]
pinctrl: tegra: remove redundant data table fields
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel
options has the relevant HW register fields in the same register as the
mux function selection. Similarly, the drvtype option is always in the
drive register, if it is supported at all. Hence, we don't need to have
struct *_reg fields in the pin group table to define which register and
bank to use for those options. Delete this to save space in the driver's
data tables.
However, many of those options are not supported on all SoCs, or not
supported on some pingroups. We need a way to detect when they are
supported. Previously, this was indicated by setting the struct *_reg
field to -1. With the struct *_reg fields removed, we use the struct
*_bit fields for this purpose instead. The struct *_bit fields need to
be expanded from 5 to 6 bits in order to store a value outside the valid
HW bit range of 0..31.
Even without removing the struct *_reg fields, we still need to add code
to validate the struct *_bit fields, since some struct *_bit fields were
already being set to -1, without an option-specific struct *_reg field to
"guard" them. In other words, before this change, the pinmux driver might
allow some unsupported options to be written to HW.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Ténart [Thu, 10 Apr 2014 13:07:50 +0000 (15:07 +0200)]
pinctrl: allows not to define the get_group_pins operation
When using a group only pinctrl driver, which does not have any
information on the pins it is useless to define a get_group_pins
always returning an empty list of pins.
When not using get_group_pin[1], a driver must implement it so
pins = NULL and num_pins = 0. This patch makes it the default
behaviour if not defined in the pinctrl driver when used in
pinmux enable and disable funtions and in pinctrl_groups_show.
It also adds a check in pinctrl_get_group_pins and return -EINVAL if
not defined. This function is called in the gpiolib when adding when
pingroup range. It cannot be used if no group is defined, so this seams
reasonable.
Boris BREZILLON [Thu, 10 Apr 2014 13:52:43 +0000 (15:52 +0200)]
pinctrl: sunxi: support multiple pin controller
Add support for multiple pin controller instances.
First remove the static definition of the sunxi gpio chip struct and fill
the dynamically struct instead.
Then define a new pin_base field in the sunxi_pinctrl_desc which will be
used to specify the gpiochip base pin.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groups
The DU parallel interface ODDF signal is optional, move it out of the
HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are
independent, split them to two different groups.
pinctrl: msm8x74: make Kconfig dependency more strict
This driver is only useful on MSM8x74, so let the driver depend on
ARCH_QCOM but allow compile coverage testing.
The main benefit is that the driver isn't available to be selected for
machines that don't have the matching hardware.
Bjorn Andersson [Mon, 31 Mar 2014 21:49:55 +0000 (14:49 -0700)]
pinctrl: msm: Make number of functions variable
The various pins may have different number of functions defined, so make this
number definable per pin instead of just increasing it to the largest one for
all of the platforms.
This lets the gpiolib core handle the irqchip set-up and
chained IRQ on the primary (behind the mux) IRQ chip in
the st pinctrl driver.
Default irq type is set to level low at irqchip add time.
The v1 was sent by Linus
(https://lkml.org/lkml/2014/4/4/287).
Two changes were necessary to make it to work properly
on STiH416:
1 - dev reference was not passed to the gpio_chip
struct, causing a panic.
2 - gpiochip_irqchip_add passed IRQ_TYPE_NONE as
default type, which caused lot of warnings at
init time. I choose IRQ_TYPE_LEVEL_LOW as default.
Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Maxime COQUELIN <maxime.coquelin@st.com>
Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
Pull slave-dmaengine fixes from Vinod Koul:
"Back from long weekend here in India and now the time to send fixes
for slave dmaengine.
- Dan's fix of sirf xlate code
- Jean's fix for timberland
- edma fixes by Sekhar for SG handling and Yuan for changing init
call"
* 'fixes' of git://git.infradead.org/users/vkoul/slave-dma:
dma: fix eDMA driver as a subsys_initcall
dmaengine: sirf: off by one in of_dma_sirfsoc_xlate()
platform: Fix timberdale dependencies
dma: edma: fix incorrect SG list handling
Merge tag 'iommu-fixes-v3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
"Fixes for regressions:
- fix wrong IOMMU enumeration causing some SCSI device drivers
initialization failures
- ARM-SMMU fixes for a panic condition and a wrong return value"
* tag 'iommu-fixes-v3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/arm-smmu: fix panic in arm_smmu_alloc_init_pte
iommu/arm-smmu: Return 0 on unmap failure
iommu/vt-d: fix bug in matching PCI devices with DRHD/RMRR descriptors
iommu/vt-d: Fix get_domain_for_dev() handling of upstream PCIe bridges
iommu/vt-d: fix memory leakage caused by commit ea8ea46
Adrien BAK [Fri, 18 Apr 2014 02:00:43 +0000 (11:00 +0900)]
perf tools: Improve error reporting
In the current version, when using perf record, if something goes
wrong in tools/perf/builtin-record.c:375
session = perf_session__new(file, false, NULL);
The error message:
"Not enough memory for reading per file header"
is issued. This error message seems to be outdated and is not very
helpful. This patch proposes to replace this error message by
"Perf session creation failed"
I believe this issue has been brought to lkml:
https://lkml.org/lkml/2014/2/24/458
although this patch only tackles a (small) part of the issue.
Additionnaly, this patch improves error reporting in
tools/perf/util/data.c open_file_write.
Currently, if the call to open fails, the user is unaware of it.
This patch logs the error, before returning the error code to
the caller.
Reported-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Adrien BAK <adrien.bak@metascale.org> Link: http://lkml.kernel.org/r/1397786443.3093.4.camel@beast
[ Reorganize the changelog into paragraphs ]
[ Added empty line after fd declaration in open_file_write ] Signed-off-by: Jiri Olsa <jolsa@redhat.com>
Signed-off-by: Vladimir Nikulichev <nvs@tbricks.com> Tested-by: Namhyung Kim <namhyung@kernel.org> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Link: http://lkml.kernel.org/r/969812.163009436-sendEmail@nvs Signed-off-by: Jiri Olsa <jolsa@redhat.com>
perf kvm: Fix 'Min time' counting in report command
Every event in the perf-kvm has a 'stats' structure, which contains
max/min/average/etc times of handling this event.
The problem is that the 'perf-kvm stat report' command always shows
that 'min time' is 0us for every event. Example:
This happens because the 'stats' structure is not initialized and
stats->min equals to 0. Lets initialize the structure for every
event after its allocation using init_stats() function. This initializes
stats->min to -1 and makes 'Min time' statistics counting work:
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Unfortunately this contains no easter eggs, its a bit larger than I'd
like, but I included a patch that just moves code from one file to
another and I'd like to avoid merge conflicts with that later, so it
makes it seem worse than it is,
Otherwise:
- radeon: fixes to use new microcode to stabilise some cards, use
some common displayport code, some runtime pm fixes, pll regression
fixes
- i915: fix for some context oopses, a warn in a used path, backlight
fixes
- nouveau: regression fix
- omap: a bunch of fixes"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (51 commits)
drm: bochs: drop unused struct fields
drm: bochs: add power management support
drm: cirrus: add power management support
drm: Split out drm_probe_helper.c from drm_crtc_helper.c
drm/plane-helper: Don't fake-implement primary plane disabling
drm/ast: fix value check in cbr_scan2
drm/nouveau/bios: fix a bit shift error introduced by 457e77b
drm/radeon/ci: make sure mc ucode is loaded before checking the size
drm/radeon/si: make sure mc ucode is loaded before checking the size
drm/radeon: improve PLL params if we don't match exactly v2
drm/radeon: memory leak on bo reservation failure. v2
drm/radeon: fix VCE fence command
drm/radeon: re-enable mclk dpm on R7 260X asics
drm/radeon: add support for newer mc ucode on CI (v2)
drm/radeon: add support for newer mc ucode on SI (v2)
drm/radeon: apply more strict limits for PLL params v2
drm/radeon: update CI DPM powertune settings
drm/radeon: fix runpm handling on APUs (v4)
drm/radeon: disable mclk dpm on R7 260X
drm/tegra: Remove gratuitous pad field
...
Dave Airlie [Sat, 19 Apr 2014 01:16:02 +0000 (11:16 +1000)]
Merge branch 'drm-next-3.15-wip' of git://people.freedesktop.org/~deathsimple/linux into drm-next
Some i2c fixes over DisplayPort.
* 'drm-next-3.15-wip' of git://people.freedesktop.org/~deathsimple/linux:
drm/radeon: Improve vramlimit module param documentation
drm/radeon: fix audio pin counts for DCE6+ (v2)
drm/radeon/dp: switch to the common i2c over aux code
drm/dp/i2c: Update comments about common i2c over dp assumptions (v3)
drm/dp/i2c: send bare addresses to properly reset i2c connections (v4)
drm/radeon/dp: handle zero sized i2c over aux transactions (v2)
drm/i915: support address only i2c-over-aux transactions
drm/tegra: dp: Support address-only I2C-over-AUX transactions
1) Fix mlx4_en_netpoll implementation, it needs to schedule a NAPI
context, not synchronize it. From Chris Mason.
2) Ipv4 flow input interface should never be zero, it should be
LOOPBACK_IFINDEX instead. From Cong Wang and Julian Anastasov.
3) Properly configure MAC to PHY connection in mvneta devices, from
Thomas Petazzoni.
4) sys_recv should use SYSCALL_DEFINE. From Jan Glauber.
5) Tunnel driver ioctls do not use the correct namespace, fix from
Nicolas Dichtel.
6) Fix memory leak on seccomp filter attach, from Kees Cook.
7) Fix lockdep warning for nested vlans, from Ding Tianhong.
8) Crashes can happen in SCTP due to how the auth_enable value is
managed, fix from Vlad Yasevich.
9) Wireless fixes from John W Linville and co.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (45 commits)
net: sctp: cache auth_enable per endpoint
tg3: update rx_jumbo_pending ring param only when jumbo frames are enabled
vlan: Fix lockdep warning when vlan dev handle notification
seccomp: fix memory leak on filter attach
isdn: icn: buffer overflow in icn_command()
ip6_tunnel: use the right netns in ioctl handler
sit: use the right netns in ioctl handler
ip_tunnel: use the right netns in ioctl handler
net: use SYSCALL_DEFINEx for sys_recv
net: mdio-gpio: Add support for separate MDI and MDO gpio pins
net: mdio-gpio: Add support for active low gpio pins
net: mdio-gpio: Use devm_ functions where possible
ipv4, route: pass 0 instead of LOOPBACK_IFINDEX to fib_validate_source()
ipv4, fib: pass LOOPBACK_IFINDEX instead of 0 to flowi4_iif
mlx4_en: don't use napi_synchronize inside mlx4_en_netpoll
net: mvneta: properly configure the MAC <-> PHY connection in all situations
net: phy: add minimal support for QSGMII PHY
sfc:On MCDI timeout, issue an FLR (and mark MCDI to fail-fast)
mwifiex: fix hung task on command timeout
mwifiex: process event before command response
...
Merge branch 'for-next' of git://git.samba.org/sfrench/cifs-2.6
Pull cifs fixes from Steve French:
"A set of 5 small cifs fixes"
* 'for-next' of git://git.samba.org/sfrench/cifs-2.6:
cif: fix dead code
cifs: fix error handling cifs_user_readv
fs: cifs: remove unused variable.
Return correct error on query of xattr on file with empty xattrs
cifs: Wait for writebacks to complete before attempting write.
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