Use the correct api in probe to enable runtime pm for this driver.
Additionally, do not just call legacy suspend for runtime_suspend,
as this duplicates some work the pci core does for you.
Signed-off-by: Kristen Carlson Accardi <kristen@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Viresh Kumar [Thu, 24 Mar 2011 06:02:15 +0000 (11:32 +0530)]
dmaengine/dw_dmac fix: dwc_scan_descriptors must compare first desc address also with llp
dwc_scan_descriptors scans all descriptors from active_list in case transfer is
not completed. It compares first_desc->lli.llp, and then all childrens of its
tx_list. But it doesn't compare its own address, i.e. first_desc->txd.phys, as
this is what we have initially programmed into the controller register. So this
causes dma to stop and finish a transfer, which was never started. And thus
fail.
Jamie Iles [Tue, 22 Mar 2011 22:34:56 +0000 (15:34 -0700)]
avr32: at32ap700x: fix typo in DMA master configuration
Commit 4aa5f366431fe (avr32: at32ap700x: specify DMA src and dst
masters) specified the masters for the ac97c playback device
but incorrectly set them in the capture slave information rather
than playback.
Cc: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Reported-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Vinod Koul <vinod.koul@intel.com>
[rebased on dmaengine for 2.6.39 (d42efe6b)] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Viresh Kumar [Tue, 22 Mar 2011 11:57:25 +0000 (17:27 +0530)]
dmaengine/dmatest: Pass timeout via module params
When we try to test all channels present on our controller together, some
channels of lower priority may be very slow as compared to others. If number of
transfers is unlimited, some channels may timeout and will not finish within 3
seconds. Thus, while doing such regress testing we may need to have higher value
of timeouts. This patch adds support for passing timeout value via module
parameters. Default value is 3 msec, a negative value means max timeout
possible.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Ira Snyder [Thu, 3 Mar 2011 07:55:01 +0000 (07:55 +0000)]
fsldma: make halt behave nicely on all supported controllers
The original dma_halt() function set the CA (channel abort) bit on both
the 83xx and 85xx controllers. This is incorrect on the 83xx, where this
bit means TEM (transfer error mask) instead. The 83xx doesn't support
channel abort, so we only do this operation on 85xx.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Ira Snyder [Thu, 3 Mar 2011 07:55:00 +0000 (07:55 +0000)]
fsldma: reduce locking during descriptor cleanup
This merges the fsl_chan_ld_cleanup() function into the dma_do_tasklet()
function to reduce locking overhead. In the best case, we will be able
to keep the DMA controller busy while we are freeing used descriptors.
In all cases, the spinlock is grabbed two times fewer than before on
each transaction.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Ira Snyder [Thu, 3 Mar 2011 07:54:59 +0000 (07:54 +0000)]
fsldma: support async_tx dependencies and automatic unmapping
Previous to this patch, the dma_run_dependencies() function has been
called while holding desc_lock. This function can call tx_submit() for
other descriptors, which may try to re-grab the lock. Avoid this by
moving the descriptors to be cleaned up to a temporary list, and
dropping the lock before cleanup.
At the same time, add support for automatic unmapping of src and dst
buffers, as offered by the DMAEngine API.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Ira Snyder [Thu, 3 Mar 2011 07:54:58 +0000 (07:54 +0000)]
fsldma: fix controller lockups
Enabling poisoning in the dmapool API quickly showed that the DMA
controller was fetching descriptors that should not have been in use.
This has caused intermittent controller lockups during testing.
I have been unable to figure out the exact set of conditions which cause
this to happen. However, I believe it is related to the driver using the
hardware registers to track whether the controller is busy or not. The
code can incorrectly decide that the hardware is idle due to lag between
register writes and the hardware actually becoming busy.
To fix this, the driver has been reworked to explicitly track the state
of the hardware, rather than try to guess what it is doing based on the
register values.
This has passed dmatest with 10 threads per channel, 100000 iterations
per thread several times without error. Previously, this would fail
within a few seconds.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Ira Snyder [Thu, 3 Mar 2011 07:54:55 +0000 (07:54 +0000)]
fsldma: use channel name in printk output
This makes debugging the driver much easier when multiple channels are
running concurrently. In addition, you can see how much descriptor
memory each channel has allocated via the dmapool API in sysfs.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Dan Williams [Fri, 11 Mar 2011 22:56:58 +0000 (14:56 -0800)]
Merge branch 'for_dan' of git://git.infradead.org/users/vkoul/slave-dma into dmaengine
* 'for_dan' of git://git.infradead.org/users/vkoul/slave-dma:
drivers, pch_dma: Fix warning when CONFIG_PM=n.
dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel
avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msize
dw_dmac: Setting Default Burst length for transfers as 16.
dw_dmac: Allow src/dst msize & flow controller to be configured at runtime
dw_dmac: Changing type of src_master and dest_master to u8.
dw_dmac: Pass Channel Priority from platform_data
dw_dmac: Pass Channel Allocation Order from platform_data
dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finish
dw_dmac: Change value of DWC_MAX_COUNT to 4095.
dw_dmac: Adding support for 64 bit access width for memcpy xfers
dw_dmac: Calling dwc_scan_descriptors from dwc_tx_status() after taking lock
dw_dmac: Move single descriptor from dwc->queue to dwc->active_list in dwc_complete_all
dw_dmac: Replace module_init() with subsys_initcall()
dw_dmac: Remove compilation dependency from AVR32 and put on HAVE_CLK
dmaengine: mxs-dma: add dma support for i.MX23/28
pch_dma: set the number of array correctly
pch_dma: fix kernel error issue
Viresh Kumar [Fri, 4 Mar 2011 09:28:32 +0000 (14:58 +0530)]
dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel
On ARMv7 cores, device memory mapped as Normal Non-cacheable, may not guarantee
ordered access causing failures in device drivers that do not use the mandatory
memory barriers. readl & writel versions contain necessary memory barriers for
this.
commit 79f64dbf68c8a9779a7e9a25e0a9f0217a25b57a: "ARM: 6273/1: Add barriers to
the I/O accessors if ARM_DMA_MEM_BUFFERABLE" can be referred for more
information on this.
Viresh Kumar [Thu, 3 Mar 2011 10:17:26 +0000 (15:47 +0530)]
avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msize
Now that the dw_dmac DMA driver supports configurable Flow Controller, source
and destination burst or msize, we need to specify which ones to use. Msize or
burst size was previously hardcoded to 1, Flow controller was DMA for both
M2P & P2M transfers.
Viresh KUMAR [Fri, 4 Mar 2011 10:12:51 +0000 (15:42 +0530)]
dw_dmac: Allow src/dst msize & flow controller to be configured at runtime
Msize or Burst Size is peripheral dependent in case of prep_slave_sg and
cyclic_prep transfers, and in case of memcpy transfers it is platform dependent.
So msize configuration must come from platform data.
Also some peripherals (ex: JPEG), need to be flow controller for dma transfers,
so this information in case of slave_sg & cyclic_prep transfers must come from
platform data.
Viresh Kumar [Thu, 3 Mar 2011 10:17:23 +0000 (15:47 +0530)]
dw_dmac: Changing type of src_master and dest_master to u8.
src_master & dest_master don't required u32 as they have values limited to u8
only. Also their description is missing from doc style comment. This patch
fixes above mentioned issues.
Viresh Kumar [Thu, 3 Mar 2011 10:17:22 +0000 (15:47 +0530)]
dw_dmac: Pass Channel Priority from platform_data
In Synopsys designware, channel priority is programmable. This patch adds
support for passing channel priority through platform data. By default Ascending
channel priority will be followed, i.e. channel 0 will get highest priority and
channel 7 will get lowest.
Viresh Kumar [Thu, 3 Mar 2011 10:17:21 +0000 (15:47 +0530)]
dw_dmac: Pass Channel Allocation Order from platform_data
In SPEAr Platform channels 4-7 have more Fifo depth. So we must get better
channel first. This patch introduces concept of channel allocation order in
dw_dmac. If user doesn't pass anything or 0, than normal (ascending) channel
allocation will follow, else channels will be allocated in descending order.
Viresh Kumar [Thu, 3 Mar 2011 10:17:20 +0000 (15:47 +0530)]
dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finish
dwc_desc_get checks all descriptors for DMA_CTRL_ACK before allocating them for
transfers. And descriptors are not marked with DMA_CRTL_ACK after transfer
finishes. Thus descriptor once used is not usable again. This patch marks
descriptors with DMA_CRTL_ACK after dma xfer finishes
Viresh Kumar [Thu, 3 Mar 2011 10:17:17 +0000 (15:47 +0530)]
dw_dmac: Calling dwc_scan_descriptors from dwc_tx_status() after taking lock
Lock must be taken before calling dwc_scan_descriptors, as this may
access/modify shared data and queues. dwc_tx_status wasn't taking lock before
calling this routine. This patch add code that takes lock before calling
dwc_scan_descriptors.
Viresh Kumar [Thu, 3 Mar 2011 10:17:16 +0000 (15:47 +0530)]
dw_dmac: Move single descriptor from dwc->queue to dwc->active_list in dwc_complete_all
dwc_complete_all and other routines was removing all descriptors from dwc->queue
and pushing them to dwc->active_list. Only one was required to be removed. Also
we are calling dwc_dostart, once list is fixed.
Viresh Kumar [Thu, 3 Mar 2011 10:17:15 +0000 (15:47 +0530)]
dw_dmac: Replace module_init() with subsys_initcall()
In some cases users of dw_dmac are initialized before dw_dmac, and if they try
to use dw_dmac, they simply fail. So its better we register init() routine
of driver using subsys_initcall() instead of module_init(), so that dma driver
is available at the earliest possible.
Viresh Kumar [Thu, 3 Mar 2011 10:17:14 +0000 (15:47 +0530)]
dw_dmac: Remove compilation dependency from AVR32 and put on HAVE_CLK
This driver will now be used in atleast two platforms AVR32 & ARM. And there is
no actual hardware dependency of this driver over AVR32 or ARM. So this
dependency can be removed altogether.
Also dw_dmac driver uses clk framework and must have compilation dependency on
HAVE_CLK
Shawn Guo [Sat, 26 Feb 2011 16:47:42 +0000 (00:47 +0800)]
dmaengine: mxs-dma: add dma support for i.MX23/28
This patch adds dma support for Freescale MXS-based SoC i.MX23/28,
including apbh-dma and apbx-dma.
* apbh-dma and apbx-dma are supported in the driver as two mxs-dma
instances.
* apbh-dma is different between mx23 and mx28, hardware version
register is used to differentiate.
* mxs-dma supports pio function besides data transfer. The driver
uses dma_data_direction DMA_NONE to identify the pio mode, and
steals sgl and sg_len to get pio words and numbers from clients.
* mxs dmaengine has some very specific features, like sense function
and the special NAND support (nand_lock, nand_wait4ready). These
are too specific to implemented in generic dmaengine driver.
* The driver refers to imx-sdma and only a single descriptor is
statically assigned to each channel.
Dan Williams [Mon, 14 Feb 2011 08:42:08 +0000 (00:42 -0800)]
dmaengine: add slave-dma maintainer
Slave-dma has become the predominant usage model for dmaengine and needs
special attention. Memory-to-memory dma usage cases will continue to be
maintained by Dan.
Cc: Alan Cox <alan@linux.intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
dma: ipu_idmac: do not lose valid received data in the irq handler
Currently when two or more buffers are queued by the camera driver
and so the double buffering is enabled in the idmac, we lose one
frame comming from CSI since the reporting of arrival of the first
frame is deferred by the DMAIC_7_EOF interrupt handler and reporting
of the arrival of the last frame is not done at all. So when requesting
N frames from the image sensor we actually receive N - 1 frames in
user space.
The reason for this behaviour is that the DMAIC_7_EOF interrupt
handler misleadingly assumes that the CUR_BUF flag is pointing to the
buffer used by the IDMAC. Actually it is not the case since the
CUR_BUF flag will be flipped by the FSU when the FSU is sending the
<TASK>_NEW_FRM_RDY signal when new frame data is delivered by the CSI.
When sending this singal, FSU updates the DMA_CUR_BUF and the
DMA_BUFx_RDY flags: the DMA_CUR_BUF is flipped, the DMA_BUFx_RDY
is cleared, indicating that the frame data is beeing written by
the IDMAC to the pointed buffer. DMA_BUFx_RDY is supposed to be
set to the ready state again by the MCU, when it has handled the
received data. DMAIC_7_CUR_BUF flag won't be flipped here by the
IPU, so waiting for this event in the EOF interrupt handler is wrong.
Actually there is no spurious interrupt as described in the comments,
this is the valid DMAIC_7_EOF interrupt indicating reception of the
frame from CSI.
The patch removes code that waits for flipping of the DMAIC_7_CUR_BUF
flag in the DMAIC_7_EOF interrupt handler. As the comment in the
current code denotes, this waiting doesn't help anyway. As a result
of this removal the reporting of the first arrived frame is not
deferred to the time of arrival of the next frame and the drivers
software flag 'ichan->active_buffer' is in sync with DMAIC_7_CUR_BUF
flag, so the reception of all requested frames works.
This has been verified on the hardware which is triggering the
image sensor by the programmable state machine, allowing to
obtain exact number of frames. On this hardware we do not tolerate
losing frames.
This patch also removes resetting the DMA_BUFx_RDY flags of
all channels in ipu_disable_channel() since transfers on other
DMA channels might be triggered by other running tasks and the
buffers should always be ready for data sending or reception.
Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Shawn Guo [Wed, 19 Jan 2011 21:50:39 +0000 (05:50 +0800)]
dmaengine: imx-sdma: fix up param for the last BD in sdma_prep_slave_sg()
As per the reference manual, bit "L" should be set while bit "C"
should be cleared for the last buffer descriptor in the non-cyclic
chain, so that sdma can stop trying to find the next BD and end
the transfer.
In case of sdma_prep_slave_sg(), BD_LAST needs to be set and BD_CONT
be cleared for the last BD.
Shawn Guo [Wed, 19 Jan 2011 21:50:38 +0000 (05:50 +0800)]
dmaengine: imx-sdma: correct sdmac->status in sdma_handle_channel_loop()
sdma_handle_channel_loop() is the handler of cyclic tx. One period
success does not really mean the success of the tx. Instead of
DMA_SUCCESS, DMA_IN_PROGRESS should be the one to tell.
Shawn Guo [Wed, 19 Jan 2011 21:50:37 +0000 (05:50 +0800)]
dmaengine: imx-sdma: return sdmac->status in sdma_tx_status()
The sdmac->status was designed to reflect the status of the tx,
so simply return it in sdma_tx_status(). Then dma client can call
dma_async_is_tx_complete() to know the status of the tx.
Shawn Guo [Wed, 19 Jan 2011 21:50:36 +0000 (05:50 +0800)]
dmaengine: imx-sdma: set sdmac->status to DMA_ERROR in err_out of sdma_prep_slave_sg()
sdma_prep_dma_cyclic() sets sdmac->status to DMA_ERROR in err_out,
and sdma_prep_slave_sg() needs to do the same. Otherwise,
sdmac->status stays at DMA_IN_PROGRESS, which will make the function
return immediately next time it gets called.
Shawn Guo [Wed, 19 Jan 2011 21:50:35 +0000 (05:50 +0800)]
dmaengine: imx-sdma: remove IMX_DMA_SG_LOOP handling in sdma_prep_slave_sg()
This is a leftover from the time that the driver did not have
sdma_prep_dma_cyclic callback and implemented sound dma as a looped
sg chain. And it can be removed now.
Sascha Hauer [Mon, 31 Jan 2011 09:56:58 +0000 (10:56 +0100)]
dmaengine i.MX SDMA: reserve channel 0 by not registering it
We need channel 0 of the sdma engine for internal purposes. We
accomplished this by calling dma_request_channel() in the probe
function. This does not work when multiple dma engines are
present which is the case when IPU support for i.MX31/35 is
compiled in. So instead of registering channel 0 and reserving
it afterwards simply do not register it in the first place.
With this the dmaengine channel counting does not match sdma
channel counting anymore, so we have to use sdma channel counting
in the driver.
Sascha Hauer [Wed, 12 Jan 2011 12:02:28 +0000 (13:02 +0100)]
dmaengine i.MX sdma: check sg entries for valid addresses and lengths
This patch lets sdma_prep_slave_sg fail if the entries of an
sg list do not start on multiples of the word size or if the
lengths are not multiple of the word size.
Also, catch the previously unhandled DMA_SLAVE_BUSWIDTH_8_BYTES
and DMA_SLAVE_BUSWIDTH_UNDEFINED cases.
Rabin Vincent [Tue, 25 Jan 2011 10:18:35 +0000 (11:18 +0100)]
dma40: cyclic xfer support
Support cyclic transfers, which are useful for ALSA drivers.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:34 +0000 (11:18 +0100)]
dma40: stop ongoing transfers in DMA_TERMINATE_ALL
The current implementation of DMA_TERMINATE_ALL leaves ongoing transfers
running. Fix it.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:33 +0000 (11:18 +0100)]
dma40: fix DMA_SG capability and channels
The DMA_SG cap is enabled on the wrong channel, and the pointers are repeatedly
set incorrectly. Fix it and combine the ops settings to a common function.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:32 +0000 (11:18 +0100)]
dma40: handle failure to allocate first LCLA
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:31 +0000 (11:18 +0100)]
dma40: extract lcla code into separate function
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:30 +0000 (11:18 +0100)]
dma40: use flags to reduce parameter count
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:29 +0000 (11:18 +0100)]
dma40: make d40_log_buf_to_lli static
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:28 +0000 (11:18 +0100)]
dma40: unify src/dst addr check
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:27 +0000 (11:18 +0100)]
dma40: pass the info pointer all the way to reduce argument count
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:26 +0000 (11:18 +0100)]
dma40: unify d40_log_sg_to_lli funcs for mem and slave
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:25 +0000 (11:18 +0100)]
dma40: combine duplicated code in log_sg_to_dev
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:24 +0000 (11:18 +0100)]
dma40: move lli_load to main source file
These register writes are better placed in the main source file rather than
ll.c.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:23 +0000 (11:18 +0100)]
dma40: combine mem and slave prep_sg functions
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:22 +0000 (11:18 +0100)]
dma40: remove export of stedma40_memcpy_sg
The dmaengine framework has the API for this now.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:21 +0000 (11:18 +0100)]
dma40: combine mem and slave sg-to-lli functions
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:20 +0000 (11:18 +0100)]
dma40: remove duplicated dev addr code
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:18 +0000 (11:18 +0100)]
dma40: combine desc init functions
The desc init code can be shared between the mem and slave prep routines.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:17 +0000 (11:18 +0100)]
dma40: implement prep_memcpy as a wrapper around memcpy_sg
To simplify the code.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:16 +0000 (11:18 +0100)]
dma40: remove unnecessary casts
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:15 +0000 (11:18 +0100)]
dma40: fix DMA API usage for LLIs
Map and unmap the LLIs and use dma_sync_single_for_device() appropriately
instead of mapping and never unmapping them.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:14 +0000 (11:18 +0100)]
dma40: fix DMA API usage for LCLA
Map the buffer once and use dma_sync*() appropriately instead of mapping the
buffer over and over without unmapping it.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:13 +0000 (11:18 +0100)]
dma40: use sg_dma_address() instead of sg_phys()
The address to use for DMA should be taken from sg_dma_address() and not
sg_phys().
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:12 +0000 (11:18 +0100)]
dma40: remove unnecessary ALIGN()s
ALIGN(x * y, y) == x * y
ALIGN(aligned + x * y, y) == aligned + x * y
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:11 +0000 (11:18 +0100)]
dma40: allow realtime and priority for event lines
DB8500v2's DMA40 (revision 3) allows setting event lines as high priority and
real time.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:10 +0000 (11:18 +0100)]
dma40: fix comment to refer to SOCs rather than boards
And add DB8500v2 information.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:09 +0000 (11:18 +0100)]
dma40: use helpers for error functions
Almost every use of dev_err in this driver prints the function name. Abstract
out wrappers to help with this and reduce code duplication.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:08 +0000 (11:18 +0100)]
dma40: use helpers for channel type check
The somewhat confusing check
d40c->log_num == D40_PHY_CHAN
and its variants are used in several places to check if a channel is logical or
physical. Use appropriately named helpers to do this to make the code more
readable.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:07 +0000 (11:18 +0100)]
dma40: use helper for channel registers base
The register offset computation for accessing channel registers is copy/pasted
in several places. Create a helper function to do it.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:06 +0000 (11:18 +0100)]
dma40: remove "hardware link with previous jobs" code
This link in hardware with previous jobs code is:
- unused, no clients using or requiring this feature
- incomplete, being implemented only for physical channels
- broken, only working to perform one link
Remove it. This also allows us to get rid of the channel pause in the
submit_tx() routine.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:05 +0000 (11:18 +0100)]
dma40: ensure event lines get enabled
The controller sometimes fails to register the enable of the event line when
both src and dst event lines are used on the same logical channel. Implement
the recommended software workaround, which is to retry the write until it
works.
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Rabin Vincent [Tue, 25 Jan 2011 10:18:04 +0000 (11:18 +0100)]
dma40: make init function static
Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
DMA: PL08x: fix channel pausing to timeout rather than lockup
If a transfer is initiated from memory to a peripheral, then data is
fetched and the channel is marked busy. This busy status persists until
the HALT bit is set and the queued data has been transfered to the
peripheral. Waiting indefinitely after setting the HALT bit results in
system lockups. Timeout this operation, and print an error when this
happens.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
DMA: PL08x: fix infinite wait when terminating transfers
If we try to pause a channel when terminating a transfer, we could end
up spinning for it to become inactive indefinitely, and can result in
an uninterruptible wait requiring a reset to recover from.
Terminating a transfer is supposed to take effect immediately, but may
result in data loss.
To make this clear, rename the function to pl08x_terminate_phy_chan().
Also, make sure it is always consistently called - with the spinlock
held and IRQs disabled, and ensure that the TC and ERR interrupt status
is always cleared.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Jamie Iles [Fri, 21 Jan 2011 14:11:55 +0000 (14:11 +0000)]
avr32: at32ap700x: specify DMA src and dst masters
Now that the dw_dmac DMA driver supports configurable source and
destination masters we need to specify which ones to use. This was
previously hardcoded to 0 and 1 respectively in the driver.
Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Jamie Iles [Fri, 21 Jan 2011 14:11:54 +0000 (14:11 +0000)]
dmaengine/dw_dmac: provide a mechanism to indicate private devices
Some platforms (e.g. Picochip PC3XX) have multiple DMA controllers
where some may be used for slave transfers and others for general
purpose memcpy type transfers. Add a .is_private boolean to the
platform data structure so that controllers can be marked as private
so that the DMA_PRIVATE capability will be set for that controller.
Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Jamie Iles [Fri, 21 Jan 2011 14:11:53 +0000 (14:11 +0000)]
dmaengine/dw_dmac: allow src/dst masters to be configured at runtime
Some platforms have flexible mastering capabilities and this needs
to be selected at runtime. If the platform has specified private
data in the form of the dw_dma_slave then fetch the source and
destination masters from here. If this isn't present, default to
the previous of 0 and 1.
v2: cleanup whitespace
Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Jamie Iles [Fri, 21 Jan 2011 14:11:52 +0000 (14:11 +0000)]
dmaengine/dw_dmac: don't scan descriptors if no xfers in progress
Some hardware (picoChip picoXCell in particular) sometimes has
the block transfer complete bit being set for a channel after the
whole transfer has completed. If we don't have any transfers in the
active list then don't bother to scan the descriptors. This often
happens in normal operation and doesn't require the channel to be
reset.
v2: cleanup whitespace
Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Shawn Guo [Mon, 17 Jan 2011 14:39:24 +0000 (22:39 +0800)]
dmaengine: imx-sdma: fix inconsistent naming in sdma_assign_cookie()
Variable name sdma and sdmac are consistently used as the pointer to
sdma_engine and sdma_channel respectively throughout the file. The
patch fixes the inconsistency seen in function sdma_assign_cookie().
Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Sascha Hauer [Wed, 12 Jan 2011 10:18:14 +0000 (11:18 +0100)]
dmaengine i.MX SDMA: Fix firmware loading
When loading the microcode to the SDMA engine we have to use
the ram_code_start_addr found in the firmware image. The copy
in the sdma engine is not initialized correctly. This is broken
since: 5b28aa3 dmaengine i.MX SDMA: Allow to run without firmware
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
projects / linux-beck.git / log