Lucas Stach [Wed, 23 Jul 2014 17:52:39 +0000 (19:52 +0200)]
PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
Use pci_create_root_bus() similar to other PCI host controller drivers.
The main problem with pci_scan_root_bus() is that it not only creates the
root bus, but also activates all devices on the bus. This triggers PCI
device driver probe routines, which fail because resources haven't been
allocated.
To work around this we made sure that the host controller driver is probed
early and finishes resource allocation before any other device drivers are
registered. Switching to pci_create_root_bus() allows us to get rid of
this special handling.
Lucas Stach [Wed, 23 Jul 2014 17:52:38 +0000 (19:52 +0200)]
PCI: designware: Parse bus-range property from devicetree
This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.
Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found. We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.
[bhelgaas: use %pR in error message to avoid duplication] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit Kumar <mohit.kumar@st.com>
(cherry picked from commit 4f2ebe00597c44f7dc6f88a052a2981ddcf6a0b6)
Lucas Stach [Thu, 31 Jul 2014 18:16:05 +0000 (20:16 +0200)]
PCI: imx6: Put LTSSM in "Detect" state before disabling it
This fixes a boot hang observed when the bootloader already enabled the
PCIe link for its own use. The fundamental problem is that Freescale
forgot to wire up the core reset, so software doesn't have a sane way to
get the core into a defined state.
According to the DW PCIe core reference manual, configuration of the core
may only happen when the LTSSM is disabled, so this is one of the first
things we need to do. Apparently this isn't safe to do when the LTSSM is in
any state other than "detect" as we observe an instant machine hang when
trying to do so while the link is already up.
As a workaround, force LTSSM into detect state right before hitting the
disable switch. There is still a race window because the LTSSM may
transition out of "detect" before we can disable it, but it's the best
we can do for now.
The Keystone PCI controller is based on v3.65 DesignWare hardware. This
version differs from newer versions of the hardware in functional areas
discussed below that make it necessary to change dw_pcie_host_init() to
support v3.65 based PCI controller.
1. No support for ATU port. Any ATU-specific resource handling code is
to be bypassed for v3.65 h/w.
2. MSI controller uses application space to implement MSI and 32 MSI
interrupts are multiplexed over 8 IRQs to the host. Hence the code
to process MSI IRQ needs to be different. This patch allows
platform driver to provide its own irq_domain_ops ptr to
irq_domain_add_linear() through an API callback from the DesignWare
core driver.
3. MSI interrupt generation requires EP to write to the RC's
application register. So enhance the driver to allow setup of
inbound access to MSI IRQ register as a post scan bus API callback.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit KUMAR <mohit.kumar@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com> CC: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Jingoo Han <jg1.han@samsung.com> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
(cherry picked from commit b14a3d1784a9252aa3bbe0bb9d14588be32f18a1)
PCI: designware: Add MSI-related pcie_host_ops for v3.65 hardware
DesignWare v3.65 hardware implements MSI controller registers in
application space. This requires updates to the DesignWare core to
support controllers based on this older hardware.
Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit
in the application register. Also, v3.65 hardware uses the MSI_IRQ
register in application register space to raise MSI IRQ to the RC from EP.
Current code uses the standard mechanism as per PCI spec. So add
get_msi_data() to get the address of this register so common code can
work on both v3.65 and newer hardware.
[bhelgaas: changelog] Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit Kumar <mohit.kumar@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
(cherry picked from commit 2f37c5a81cff2c341fa19fdd132ece6aea30a735)
PCI: designware: Program ATU with untranslated address
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses. So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff]. For programming the outbound translation
window the *base* should be programmed as 0x00000000. Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.
This is needed when the dt node is modelled something like this:
Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000. The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mohit Kumar <mohit.kumar@st.com> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de>
(cherry picked from commit f4c55c5a3f7f68c06cc559ed7af8b2d017cbb0a7)
PCI: designware: Look for configuration space in 'reg', not 'ranges'
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address space
in the designware driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit Kumar <mohit.kumar@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de>
(cherry picked from commit 4dd964df36d0e548e1806ec2ec275b62d4dc46e8)
Lucas Stach [Tue, 3 Jun 2014 14:44:25 +0000 (08:44 -0600)]
PCI: designware: Split Exynos and i.MX bindings
The glue around the core designware IP is significantly different between
the Exynos and i.MX implementation, which is reflected in the DT bindings.
This changes the i.MX6 binding to reuse as much as possible from the common
designware binding and removes old cruft.
I removed the optional GPIOs with the following reasoning:
- disable-gpio: endpoint specific GPIO, not currently wired up in any code.
Should be handled by the PCI device driver, not the host controller
driver.
- wake-up-gpio: same as above.
- power-on-gpio: No user in any upstream DT. This should be handled by a
regulator which shouldn't be controlled by the host driver, but rather by
the PCI device driver.
[bhelgaas: whitespace fixes] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
(cherry picked from commit 1db823ee9f677e1a863cd04fda391a7520fcd0e8)
Andrew Lunn [Thu, 10 Jul 2014 21:36:29 +0000 (23:36 +0200)]
PCI: mvebu: Remove ARCH_KIRKWOOD dependency
mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu.
ARCH_MVEBU is sufficient.
Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
(cherry picked from commit c27602086d08d22b067a1267e09fb32b4b096aa0)
Pratyush Anand [Tue, 11 Feb 2014 06:09:26 +0000 (11:39 +0530)]
PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx
ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip
designware PCIe controller. To make that usable, this patch adds a wrapper
driver based on existing designware driver.
Adds bindings for this new driver and update MAINTAINERS as well.
Add support for a generic PCI host controller, such as a
firmware-initialised device with static windows or an emulation by
something such as kvmtool.
The controller itself has no configuration registers and has its address
spaces described entirely by the device-tree (using the bindings from
ePAPR). Both CAM and ECAM are supported for Config Space accesses.
Add corresponding documentation for the DT binding.
[bhelgaas: currently uses the ARM-specific pci_common_init_dev() interface] Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
(cherry picked from commit ce292991d88b77160f348fb8a3a2cf6e78f4b456)
Lucas Stach [Fri, 28 Mar 2014 16:52:58 +0000 (17:52 +0100)]
PCI: designware: Make MSI ISR shared IRQ aware
On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD. Make
sure we don't bail too early from the IRQ handler.
The issue is fairly theoretical as it would require a system setup with a
PCIe switch where one connected device is using legacy INTD and another one
using MSI, but better fix it now.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit 7f4f16eef5aeba31bdfb7702ced06a42f2777e04)
imx6_add_pcie_port() is called only from from imx6_pcie_probe() which is
annotated with __init. Thus it makes sense to annotate
imx6_add_pcie_port() with __init to avoid section mismatch warnings.
[bhelgaas: changelog] Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Sean Cross <xobs@kosagi.com>
(cherry picked from commit 44cb5e94f96cef72a977fc5fdea8095bc0ae25ba)
add_pcie_port() is called only from exynos_pcie_probe(), which is annotated
with __init. Thus it makes sense to annotate add_pcie_port() with __init
to avoid the following section mismatch warning:
WARNING: drivers/pci/built-in.o(.text.unlikely+0xf8): Section mismatch in reference from the function add_pcie_port() to the function .init.text:dw_pcie_host_init()
The function add_pcie_port() references
the function __init dw_pcie_host_init().
This is often because add_pcie_port lacks a __init
annotation or the annotation of dw_pcie_host_init is wrong.
[bhelgaas: changelog] Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com>
(cherry picked from commit 17d7acc8e1c81f8125730aa900c67412a2ac69e2)
Lucas Stach [Wed, 5 Mar 2014 13:25:51 +0000 (14:25 +0100)]
PCI: designware: Use new OF interrupt mapping when possible
Use new OF interrupt mapping (of_irq_parse_and_map_pci()) when possible.
This is the recommended method of doing the IRQ mapping. For old
devicetrees we fall back to the previous practice.
This makes INTB, INTC, and INTD work on i.MX.
Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jingoo Han <jg1.han@samsung.com>
(cherry picked from commit 804f57b1a63c7435fe43b36942581cc6c79ebb5c)
Bai Ping [Mon, 15 Dec 2014 15:56:09 +0000 (23:56 +0800)]
MLK-9996 arm: imx6: Correct the AHB clock in low_bus_freq_mode
When the busfreq is in audio_bus_freq_mode, the AHB bus is at 8MHz,
in low_bus_freq_mode, the AHB needs to run at 24MHz. So when switching
from audio_bus_freq_mode to low_bus_freq_mode, make sure the AHB is at
24MHz in low_bus_freq_mode.
Jyri Sarha [Tue, 14 Oct 2014 17:29:27 +0000 (20:29 +0300)]
ASoC: hdmi: HDMI codec doesn't benefit from pmdown delay
Adds .ignore_pmdown_time = true to codec driver struct.
HDMI codec is currently a dummy codec and doesn't benefit from pmdown
delay. Even if in the future the codec would controll HDMI encoder, it
would still be a digital to digital interface that should have no need
for pmdown delay.
Jyri Sarha [Tue, 14 Oct 2014 17:29:26 +0000 (20:29 +0300)]
ASoC: hdmi: Mark the maximum significant bits to HDMI codec
HDMI audio can not have more than 24 bits even if on i2s bus there
would be 32 bit samples. Mark this by adding .sig_bits = 24 to
playback stream definition.
Anson Huang [Thu, 4 Dec 2014 04:24:49 +0000 (12:24 +0800)]
MLK-9955-10 arm: imx: add A9-M4 power management
this patch adds A9-M4 power management, including
below features:
1. busfreq: M4 is registered as a high speed device
of A9, when M4 is running at high speed, busfreq
will NOT enter low bus mode, when M4 is entering
its low power idle, A9 will be able to enter low
bus mode according to its state machine;
2. low power idle: only when M4 is in its low power
idle, busfreq is staying at low bus mode, low
power idle is available for kernel;
3. suspend: when M4 is NOT in its low power idle,
when linux is about to suspend, it will only
force SOC enter WAIT mode, only when M4 is in
its low power idle in TCM, linux suspend can
enter DSM mode. M4 can request/release wakeup
source via MU to A9.
as M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:
M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
power idle;
4. receive interrupt to exit low power idle, send request
to A9 for increase busfreq and M4 freq, enter wfi
and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.
A9:
1. when receive M4's message of entering low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to OSC, ungate M4 clk,
send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to origin high clk,
ungate M4 clk, send ready command to wake up M4
to exit low power idle;
As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:
clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;
Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.
For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.
Allen Xu [Mon, 13 Oct 2014 23:15:35 +0000 (18:15 -0500)]
MLK-9674-3 arm: imx: add QSPI save/restore when M4 is enabled
As M4 is executing on QSPI2 flash, and QSPI is inside Mega/Fast
domain which may lost power in DSM, so we need to do save/restore
of QSPI2 controller to make sure QSPI flash can be accessed before
waking up M4 after exiting from DSM.
Signed-off-by: Allen Xu <b45815@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
Anson Huang [Thu, 4 Dec 2014 02:02:15 +0000 (10:02 +0800)]
MLK-9955-8 arm: imx: add mu driver support
add MU driver support in mach-imx, all the MU functions
and communications between A9 and M4 will be done in
this file, including MCC, shared clk/power management.
Anson Huang [Thu, 4 Dec 2014 01:58:27 +0000 (09:58 +0800)]
MLK-9955-6 arm: dts: imx6sx: add m4 dts support
1. add i.MX6SX SabreAuto board M4 dts support;
2. add shared memory node support for AMP clk/power management;
3. add qspi restore node for suspend/resume with Mega/Fast off
when M4 is enabled and running on QSPI flash.
Nimrod Andy [Thu, 11 Dec 2014 01:20:32 +0000 (09:20 +0800)]
net: fec: clear all interrupt events to support i.MX6SX
For i.MX6SX FEC controller, there have interrupt mask and event
field extension. To support all SOCs FEC, we clear all interrupt
events during MAVC initial process.
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Nimrod Andy [Thu, 11 Dec 2014 01:20:31 +0000 (09:20 +0800)]
net: fec: reset fep link status in suspend function
On some i.MX6 serial boards, phy power and refrence clock are supplied
or controlled by SOC. When do suspend/resume test, the power and clock
are disabled, so phy device link down.
For current driver, fep->link is still up status, which cause extra operation
like below code. To avoid the dumy operation, we set fep->link to down when
phy device is real down.
...
if (fep->link) {
napi_disable(&fep->napi);
netif_tx_lock_bh(ndev);
fec_stop(ndev);
netif_tx_unlock_bh(ndev);
napi_enable(&fep->napi);
fep->link = phy_dev->link;
status_change = 1;
}
...
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Fugang Duan [Wed, 10 Dec 2014 05:46:08 +0000 (13:46 +0800)]
MLK-9919 net: fec: reinit MAC0 MII bus for MAC1 use after resume back
i.MX6SX-AI board has two enet MACs (MAC0 and MAC1), they share MAC0 MII
bus. When PHY0 don't connect to enet MAC0, MAC0 mii bus probe phy0 failed,
and the net interface is set to unattach mode. During suspend resume test,
driver don't reinit MAC0 after resume back, so MII bus don't work that causes
MAC1 also cannot access PHY1.
The patch just is workaround that reinit MAC0 MII bus for MAC1 using.
Fugang Duan [Mon, 13 Oct 2014 09:17:27 +0000 (17:17 +0800)]
MLK-9977 ARM: dts: imx6sx: specify the phy address
Since fec controller contain mdio bus, for imx serial chips, there have
no independent/external MDIO bus. ENET1 and ENET2 share use ENET1 mdio bus.
So, specify the phy address for two MACs.
The current enet RGMII TXCLK rise/fall time which could be observed(~0.85ns)
is longer than requirement (<=0.75ns).
The current setting, SPEED/DSE/SRE=10/110/1 is used, and then it needs to
increase DSE to 111 "37 Ohm @ 3.3V, 21 Ohm@1.8V, 34 Ohm for DDR". After the
change RGMII TXCLK match the spec requirement.
Robin Gong [Mon, 8 Dec 2014 09:30:40 +0000 (17:30 +0800)]
MLK-9768: dma: imx-sdma: fix UART loopback random failed
For UART, we need use old chn_real_count to know the real rx count even in
cylic dma mode, because UART driver use cyclic mode to increase performance
without any data loss.
Fugang Duan [Mon, 8 Dec 2014 09:05:32 +0000 (17:05 +0800)]
net: fec: init maximum receive buffer size for ring1 and ring2
i.MX6SX fec support three rx ring1, the current driver lost to init
ring1 and ring2 maximum receive buffer size, that cause receving
frame date length error. The driver reports "rcv is not +last" error
log in user case.
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Lothar Waßmann [Mon, 17 Nov 2014 09:51:22 +0000 (10:51 +0100)]
net: fec: use swab32s() instead of cpu_to_be32()
when swap_buffer() is being called, we know for sure, that we need to
byte swap the data. Furthermore, this function is called for swapping
data in both directions. Thus cpu_to_be32() is semantically not
correct for all use cases. Use swab32s() to reflect this.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: David S. Miller <davem@davemloft.net>
Lothar Waßmann [Fri, 7 Nov 2014 09:02:47 +0000 (10:02 +0100)]
net: fec: fix regression on i.MX28 introduced by rx_copybreak support
commit 1b7bde6d659d ("net: fec: implement rx_copybreak to improve rx performance")
introduced a regression for i.MX28. The swap_buffer() function doing
the endian conversion of the received data on i.MX28 may access memory
beyond the actual packet size in the DMA buffer. fec_enet_copybreak()
does not copy those bytes, so that the last bytes of a packet may be
filled with invalid data after swapping.
This will likely lead to checksum errors on received packets.
E.g. when trying to mount an NFS rootfs:
UDP: bad checksum. From 192.168.1.225:111 to 192.168.100.73:44662 ulen 36
Do the byte swapping and copying to the new skb in one go if
necessary.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Fugang Duan [Mon, 8 Dec 2014 08:27:54 +0000 (16:27 +0800)]
MLK-9828 ARM: imx: change uart clk parent to pll3_80m on i.mx6sx in default
By default, uboot set uart clk parent to OSC to make UART work when M4
is enabled. In the situation, uart maximum baud rate only reach at 1.5Mbps
that cannot match real case requirement.
The patch set the uart module clock source to pll3_80m in default. If
test low power case, it needs to add "uart_from_osc" in kernel command line.
Fugang Duan [Thu, 20 Nov 2014 09:50:41 +0000 (17:50 +0800)]
MLK-9893 tty: serial: imx: sync the completed and cur index
The current logic has one potential issue cause data buffer lost in
busy system. When sdma copy data buffer count is zero, completed index
also increase, which cause data buffer lost. The patch fix the issue.
Anson Huang [Tue, 19 Aug 2014 03:02:48 +0000 (11:02 +0800)]
ENGR00327584-1 : ARM: dts: imx6sx: add new ocram node for mega/fast save/restore
As when Mega/Fast mix power domain is off in DSM mode, ocram
need to do save/restore for entire space, some of the ocram
space is reserved by low power modules, so to make ocram save/restore
simple, we define a node including total ocram space for DSM
save/restore when mega/fast mix is off.
Shengjiu Wang [Thu, 23 Oct 2014 10:00:39 +0000 (18:00 +0800)]
MLK-9723-2: ASoC: fsl_sai: fix no frame clk in master mode
After several open/close sai test with ctrl+c, there will be I/O error.
The SAI can't work anymore, can't recover. There will be no frame clock.
With adding the software reset in trigger stop, the issue can be fixed.
Shengjiu Wang [Thu, 23 Oct 2014 09:17:30 +0000 (17:17 +0800)]
MLK-9723-1: ASoC: fsl_sai: add mclk divider function for master mode
SAI has 4 mclk source, and the divider is 8bit. fsl_sai_set_bclk will
select proper mclk source and calculate the divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and
add hw_free() to disable the mclk.
Nicolin Chen [Mon, 4 Aug 2014 07:07:25 +0000 (15:07 +0800)]
ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous Mode
There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.
And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.
So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 855675f6e6a65688a7f4cf45b9b5a98cf6c6f5c3)
Nicolin Chen [Fri, 8 Aug 2014 10:41:19 +0000 (18:41 +0800)]
ASoC: fsl_sai: Make Synchronous and Asynchronous modes exclusive
The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added
new Device Tree bindings for Asynchronous and Synchronous modes support.
However, these two shall not be present at the same time.
So this patch just simply makes them exclusive so as to avoid incorrect
Device Tree binding usage.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit ce7344a4ebabe90e064d3e087727f45624cdc942)
Nicolin Chen [Tue, 5 Aug 2014 07:32:05 +0000 (15:32 +0800)]
ASoC: fsl_sai: Add asynchronous mode support
SAI supports these operation modes:
1) asynchronous mode
Both Tx and Rx are set to be asynchronous.
2) synchronous mode (Rx sync with Tx)
Tx is set to be asynchronous, Rx is set to be synchronous.
3) synchronous mode (Tx sync with Rx)
Rx is set to be asynchronous, Tx is set to be synchronous.
4) synchronous mode (Tx/Rx sync with another SAI's Tx)
5) synchronous mode (Tx/Rx sync with another SAI's Rx)
* 4) and 5) are beyond this patch because they are related with another SAI.
As the initial version of this SAI driver, it supported 2) as default while
the others were totally missing.
So this patch just adds supports for 1) and 3).
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 08fdf65e37d560581233e06a659f73deeb3766f9)
Nicolin Chen [Mon, 4 Aug 2014 07:07:25 +0000 (15:07 +0800)]
ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous Mode
There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.
And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.
So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit af96ff5b7448dc776dc24a5c4313c6ec1ee94e53)
Nicolin Chen [Tue, 5 Aug 2014 09:20:21 +0000 (17:20 +0800)]
ASoC: fsl_sai: Initialize with software reset
This patch adds software reset code in dai_probe() so as to make a true init
by clearing SAI's internal logic, including the bit clock generation, status
flags, and FIFO pointers.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 376d1a92ca587d3974d4791cdb99baa8b8e7f0dd)
In 3f81aadd7e12ee7d83b271354b76316d31a04ffc, we set the ESAI clock route
in mach-imx6sx.c. In L3.14, as there is assigned-clks feature in devicetree,
we can set the clock route in dts file.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu Wang [Mon, 13 Oct 2014 03:47:32 +0000 (11:47 +0800)]
MLK-9684-6: ARM: clk-imx6sx: add missing lvds2 clock to the clock tree
We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
Shengjiu Wang [Mon, 13 Oct 2014 03:26:02 +0000 (11:26 +0800)]
MLK-9684-2: ASoC: imx-si476x: remove the codec_name, use the codec_of_node
As the codec_name has a suffix, which is a index and is different
for different platform or different kernel. So here change machine driver
to use codec_of_node, which can be same for different platform/kernel,
then we can maintain a same machine driver for fm.
Shengjiu Wang [Fri, 31 Oct 2014 05:51:20 +0000 (13:51 +0800)]
MLK-9731 ASoC: imx-hdmi-dma: audio output is noisy in long time playback
In the frame_to_bytes(), when hw_ptr*frame_bits exceed the maxmum of unsigned
long, the return value is saturated, so the appl_bytes is wrong.
This patch is to correct the usage of frame_to_bytes().
Shengjiu Wang [Tue, 18 Nov 2014 06:20:55 +0000 (14:20 +0800)]
MLK-9866: mfd: si476x: FM will fail to open sometimes.
In commit e856a0ebc23dcd2c933e3f902317652cc50f0067, we disabled
wait_event_timeout for CMD_POWER_DOWN, which will cause power down
failed sometimes, then FM will fail to reopen.
In this patch enable the wait_event_timeout for power down.
Shengjiu Wang [Mon, 3 Nov 2014 08:47:17 +0000 (16:47 +0800)]
MLK-9782: ASoC: fsl_esai: fix the channel swap issue in low possibility
There is very low possibility that channel swap happened in beginning when
multi output/input pin is enabled. The issue is that hardware can't send data
to correct pin in the begginning with the normal enable flow.
Here use TSMA/TSMB as the trigger for sending data to workaround this issue.
Shengjiu Wang [Wed, 29 Oct 2014 07:47:35 +0000 (15:47 +0800)]
MLK-9760: ASoC: fsl_esai: fix NULL pointer issue in reset handler
When test with case arecord -Dhw:0,1 | aplay -Dhw:0,0, xrun happened,
the reset handler will be called, but for BE(backend) stream, the
substream->ops is null.
This patch is to fix this null pointer issue.
Bai Ping [Thu, 4 Dec 2014 11:44:26 +0000 (19:44 +0800)]
MLK-9954 arm: imx: update operating point for i.MX6DL
Update the i.MX6DL cpu operating points to comply with the latest
published datasheet. Latest i.MX6DL datasheet of Rev.4, 10/2014
updates the 396MHz setpoint's min voltage from 1.075V to 1.125V, Add a
25mV margin to cover the board IR drop, here use 1.15V for 396MHz to
match datasheet.
projects / karo-tx-linux.git / log