Anssi Hannula [Sun, 15 Jun 2014 23:39:45 +0000 (02:39 +0300)]
ARM: dts: imx6: remove non-working spdif rxtx4 and rxtx6 clocks
The S/PDIF rxtx4 and rxtx6 clock inputs are "ESAI_HCKT" and "MLB clock",
respectively, according to the SoC documentation, and they are currently
mapped to clocks "esai" and "mlb".
However, they do not seem to actually work correctly. Testing on a
Cubox-i system with fsl_spdif driver forced to select one of those as
input will result in I/O errors on audio playback, which I believe means
missing clock signal.
Possibly the "ESAI_HCKT" and "MLB clock" refer to some other clocks
related to ESAI and MLB, or we are missing something else.
Since audio playback will not work if fsl_spdif selects these clocks
(which happens rarely), set the inputs do dummy clocks, at least for
now.
Signed-off-by: Anssi Hannula <anssi.hannula@iki.fi> Cc: Mark Brown <broonie@kernel.org> Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Anssi Hannula [Sun, 15 Jun 2014 23:39:44 +0000 (02:39 +0300)]
ARM: dts: imx6: remove wrong spdif rxtx2 clock
The rxtx2 clock of i.MX6 S/PDIF is currently set to "asrc" clock.
However, according to SoC documentation, rxtx2 is connected to
ASRC_EXT_CLK, a different external clock.
Testing on Cubox-i system seems to confirm that: when fsl_spdif is
forced to select rxtx2 as input clock, audio playback fails with an I/O
error.
Set rxtx2 to the dummy clock by default to prevent fsl_spdif from
selecting it.
Signed-off-by: Anssi Hannula <anssi.hannula@iki.fi> Cc: Mark Brown <broonie@kernel.org> Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Lothar Waßmann [Thu, 12 Jun 2014 13:05:17 +0000 (15:05 +0200)]
ARM: dts: imx6: add support for Ka-Ro TX6 modules
This patch adds support for the Ka-Ro electronics GmbH TX6 modules.
There are five distinct module types with either i.MX6Q or i.MX6DL and
LVDS or LCD display interface and one DTS file for a complete system
with an i.MX6DL based TX6 module and a baseboard mounted on the back
of a display (imx6dl-tx6dl-comtft.dts).
The 2.5V VDD_ETH_IO voltage supplied by the DA9063 LDO4 is used
to power the KSZ9031 PHY DVDDH input and to pull the necessary
pins (including bootstrap pins) high.
It also powers the i.MX6 NVCC_RGMII and NVCC_ENET inputs.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Tim Harvey [Thu, 22 May 2014 06:04:54 +0000 (23:04 -0700)]
ARM: dts: imx6: ventana: change sound device name
The 'model' property in the imx-audio-sgtl5000 binding specifies the
user-visible name of the audio device. This should be something common and
not baseboard specific.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
ARM: dt: imx28-cfa10036: introduce a regulator for mmc0
The PWM3 pinmux configuration conflicts with gpio 3.28. Introduce a regulator
for mmc0 so that it conflicts with the pwm driver and fails gracefully. The
kernel will then able to access mmc0 normally.
Fugang Duan [Tue, 20 May 2014 06:50:44 +0000 (14:50 +0800)]
ARM: dts: imx6sl: add fec sleep pinctrl for pin PM state
when system suspend, need to set pins to low power state to
save IO power consumption, there are three states of pinctrl:
"default", "idle" and "sleep". Currently enet supports default
and sleep state.
Fabio Estevam [Wed, 14 May 2014 19:53:55 +0000 (16:53 -0300)]
ARM: dts: imx6qdl-sabresd: Configure the ECSPI1 chip select pin
GPIO4_9 is used as ECSPI1 chip select and it needs to be configured as GPIO.
Configure the pin functionality explicitly in the dts file instead of relying
on the fact that it comes configured as GPIO from POR or from the bootloader.
The i.MX SoC changes for 3.17:
- Add devicetree support for i.MX1 and i.MX21 clock driver
- Use CLOCKSOURCE_OF_DECLARE() to initialize timer for DT targets
- Use of_clk_init() to initialize i.MX25 and i.MX27 clock driver in
device tree boot
- Remove i.MX1 camera support
- Remove i.MX27 IP Camera and Lite-Kit board support
- Add suspend and cpuidle support for i.mx6sx
- Clean up unused clk_register_clkdev() lookups
- Update imx-weim bus driver to support populating devices on a simple
bus
- Switch i.MX27 and i.MX6QDL clock driver to use macro for clock IDs
- Make i.MX51 a DT only platform and clean up the non-DT support code
- Support disabling supervisor protect via DT
- Random defconfig updates
Most peripherals on the i.MX53 have an
Off-Platform Peripheral Access Control Register (OPACR)
in which the access rights (together with the MPROT registers) can be declared.
However, this does not seem to work for example for SSI1+SDMA, because the
supervisor bit is not set for the SDMA unit.
It does work for SSI2, the QSB for example uses SSI2 for its audio. But SSI2 only
works because it does NOT have an OPACR.
The right solution would be to fix the access rights for the SDMA, but the unit
responsible for this is the Central Security Unit (CSU), which of course is NOT
documented. So, until documentation for this is openly available, turn off the
supervisor protection because it cripples the hardware.
ARM: i.MX: allow disabling supervisor protect via DT
The i.MX SoCs allow to setup fine grained access rights to peripherals on the
AIPS bus.
This is done via the Peripheral Access Register (PAR) in e.g. the i.MX21
or in later SoC versions the Off-Platform Peripheral Access Control Register
(OPACR), e.g. i.MX53.
Under certain circumstances this leads to problems in which bus masters are
not granted their access rights to peripherals.
To be able to disable these restrictions on DT platforms, add a helper function
that looks for AIPS nodes in the DT and disables them for every compatible node
it finds.
The compatible has to be declared in the mach-specific entry file, where this
helper function should then be called.
ARM: i.MX: Remove Freescale Logic Product Development i.MX27 Lite-Kit board support
The board has no insufficient support to be fully functional and seems
has no users. This patch removes support for this board.
However, the support may be added in the future by using the devicetree.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Liu Ying [Fri, 4 Jul 2014 09:00:41 +0000 (17:00 +0800)]
bus: imx-weim: populate devices on a simple bus
There could be some memory map devices located in
a certain chip select region of the i.MX WEIM.
The devices could be attached to a simple bus(for
example, a AXI bus) whose root node is one child
device tree node of the i.MX WEIM device tree node.
There should be a bridge(very likely, software
transparent) bewteen the i.MX WEIM and the simple bus.
This patch makes the i.MX WEIM driver possible to
populate devices on a simple bus. In this way, people
may try various IPs(in a FPGA, maybe) outside of i.MX
chips with the i.MX WEIM embedded.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
ARM: imx: build cpu_is_imx6sl function conditionally
imx6q_pm_enter calls imx6sl_set_wait_clk when run on an imx6sl
based machine. However if support for imx6sl is not enabled
at compile time, this prevents us from building the kernel and
we get this link error instead:
arch/arm/mach-imx/built-in.o: In function `imx6q_pm_enter':
:(.text+0x4b84): undefined reference to `imx6sl_set_wait_clk'
This makes the cpu_is_imx6sl function conditionally return false
if imx6sl is disabled at compile-time, which matches what the
older cpu_is_mx* macros did. We have similar inline functions for
the other imx6 variants, but so far I have not run into a case
where the extra #ifdef is necessary.
The PL310 integrated on i.MX6 series and VF610 are revision r3p1 and
later. Per ARM PL310 errata document, 588369 is fixed in r2p0 and
727915 is fixed in r3p1. Neither is needed for i.MX6 or VF610. So
let's drop them.
Alexander Shiyan [Sun, 22 Jun 2014 13:17:08 +0000 (17:17 +0400)]
ARM: i.MX21 clk: Cleanup driver
This is a cleanup for i.MX21 clk driver. This change includes:
- Reduce license text.
- Remove unused definitions.
- Remove unused #include and sort the rest.
- Remove useless comment.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Sun, 15 Jun 2014 11:35:10 +0000 (19:35 +0800)]
ARM: imx6qdl: switch to use macro for clock ID
Instead of using enum for clock ID, let's switch imx6qdl clock driver to
use macro. In this case, device tree can reuse these macros to improve
readability.
Alexander Shiyan [Wed, 18 Jun 2014 17:26:39 +0000 (21:26 +0400)]
ARM: i.MX: Remove Freescale i.MX27 IP Camera board support
The board has no insufficient support to be fully functional and seems
has no users. This patch removes support for this board. However, the
support may be added in the future by using the devicetree.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Alexander Shiyan [Fri, 13 Jun 2014 07:26:13 +0000 (11:26 +0400)]
ARM: i.MX system: Add a reset fallback if base address of watchdog is not set
This patch adds a reset fallback if base address of watchdog is not set.
This is intended for a targets not compatible with imx-21 watchdog,
i.MX1 for example.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Tue, 20 May 2014 07:46:46 +0000 (15:46 +0800)]
ARM: imx5: remove file mm-imx5.c
The only code left in mm-imx5.c is to create static mapping. While all
IMX platform code are moved to use dynamic mapping, the file can just be
removed now.
Shawn Guo [Tue, 20 May 2014 07:34:06 +0000 (15:34 +0800)]
ARM: imx5: move init hooks into mach-imx5x.c
These imx5 init_early[late] hooks are called only from mach-imx5x.c.
Let's move them into mach-imx5x.c.
While at it, replace the static mapping in imx51_ipu_mipi_setup() with
dynamic mapping. Also this function and imx_src_init() do not
necessarily to be called at .init_early hook, so move them into
.init_machine.
The mxc_iomux_v3_init() is dropped from imx51_init_early() in the
moving, since it's only needed by non-DT boot.
Shawn Guo [Tue, 20 May 2014 06:55:15 +0000 (14:55 +0800)]
ARM: imx5: use dynamic mapping for Cortex and GPC block
The imx5 pm code uses static mapping to access Cortex and GPC registers.
The patch create struct imx5_pm_data to encode physical address of
Cortex and GPC block, and create dynamic mapping for them at run-time.
Shawn Guo [Tue, 20 May 2014 05:41:36 +0000 (13:41 +0800)]
ARM: imx5: reuse clock CCM mapping in pm code
The imx5 pm code needs to access CCM registers. Let's remove the use
of CCM static mapping in pm code by reusing the dynamic mapping created
in clock code.
Shawn Guo [Tue, 20 May 2014 05:08:45 +0000 (13:08 +0800)]
ARM: imx5: use dynamic mapping for DPLL block
Replace the static mapping of DPLL block with dynamic mapping by
calling ioremap(). Ideally, this should be done by calling of_iomap(),
so that the physical address of DPLL can also be retrieved from device
tree. But unfortunately, DPLL blocks are not defined in DT in the first
place. So to maintain the compatibility of existing DTB, we use
ioremap() with physical address defines in the code.
Shawn Guo [Tue, 20 May 2014 03:20:28 +0000 (11:20 +0800)]
ARM: imx5: use dynamic mapping for CCM block
Replace the static mapping of CCM block with dynamic mapping and
retrieve CCM base address from device tree. Though it's not nice to
encode the variable ccm_base in macros, it helps to avoid a massive
churn on the code.
Shawn Guo [Mon, 19 May 2014 14:23:43 +0000 (22:23 +0800)]
ARM: imx5: retrieve iim base from device tree
Instead of using static define and mapping, the patch changes imx5 code
that reads chip revision from IIM to retrieve base address from device
tree and use dynamic mapping.
Shawn Guo [Mon, 19 May 2014 12:19:06 +0000 (20:19 +0800)]
ARM: imx5: tzic_init_irq() can directly be .init_irq hook
After i.MX51 supports DT only, tzic_init_irq() can figure out the
tzic_base on its own. Thus, it can directly be .init_irq hook, and
mx51[53]_init_irq() can be saved.
Shawn Guo [Mon, 19 May 2014 07:47:32 +0000 (15:47 +0800)]
ARM: imx5: drop arguments from mx5_clocks_common_init()
The function mx5_clocks_common_init() was created with a number of
arguments to pass oscillator clock rate in non-DT boot. Since i.MX5
is DT only platform, the arguments can be dropped, and the clock rate
can just be retrieved from device tree.
Shawn Guo [Mon, 19 May 2014 05:47:43 +0000 (13:47 +0800)]
ARM: imx5: drop option MACH_IMX51_DT
Since i.MX51 becomes DT only now, we can drop option MACH_IMX51_DT and
just use SOC_IMX51 instead. While at it, rename imx51-dt.c to
mach-imx51.c to align with the name schema of other IMX DT only
platforms.
Shawn Guo [Mon, 19 May 2014 05:37:50 +0000 (13:37 +0800)]
ARM: imx5: move SOC_IMX5 and SOC_IMX51 into 'Device tree only'
After moving SOC_IMX51 support over to device tree, all i.MX5 support
becomes device tree only now. So options SOC_IMX5 and SOC_IMX51 can
just be under 'Device tree only'.
While at it, 'select ARCH_MXC_IOMUX_V3' is dropped, since it's only
needed by non-DT build before.
Shawn Guo [Mon, 19 May 2014 12:41:52 +0000 (20:41 +0800)]
ARM: imx: move EHCI platform defines out of platform_data header
The platform_data header usb-ehci-mxc.h has a lot of stuff used by only
IMX platform code. They shouldn't be really in this header but a IMX
platform local header. Create ehci.h and move these stuff into it.
Alexander Shiyan [Tue, 20 May 2014 16:43:51 +0000 (20:43 +0400)]
ARM: i.MX: Remove registration helper for i.MX1 USB UDC
imx_udc driver was removed from the kernel of about 10 months ago.
This patch removes a registration helper for this driver and
orphaned driver header.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
It fixes a hard machine hang regression for boards where only pcie is
active but no sata, as the latest imx6-pcie driver is no longer enabling
the upstream clock directly but only lvds clk out.
Lucas Stach [Thu, 17 Jul 2014 10:20:14 +0000 (12:20 +0200)]
ARM: clk-imx6q: parent lvds_sel input from upstream clock gates
The i.MX6 reference manual doesn't make a clear distinction
between the fixed clock divider and the enable gate for the
pcie and sata reference clocks. This lead to the lvds mux
inputs in the imx6q clk driver to be parented from the
ref clock (which is the divider) instead of the actual gate,
which in turn prevents the upstream clock to actually be
enabled when lvds clk out is active.
This fixes a hard machine hang regression in kernel 3.16 for
boards where only pcie is active but no sata, as with this
kernel version the imx6-pcie driver is no longer enabling
the upstream clock directly but only lvds clk out.
Reported-by: Arne Ruhnau <arne.ruhnau@target-sg.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Arne Ruhnau <arne.ruhnau@target-sg.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Linus Torvalds [Sun, 29 Jun 2014 20:40:08 +0000 (13:40 -0700)]
Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King:
"Another round of ARM fixes. The largest change here is the L2 changes
to work around problems for the Armada 37x/380 devices, where most of
the size comes down to comments rather than code.
The other significant fix here is for the ptrace code, to ensure that
rewritten syscalls work as intended. This was pointed out by Kees
Cook, but Will Deacon reworked the patch to be more elegant.
The remainder are fairly trivial changes"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8087/1: ptrace: reload syscall number after secure_computing() check
ARM: 8086/1: Set memblock limit for nommu
ARM: 8085/1: sa1100: collie: add top boot mtd partition
ARM: 8084/1: sa1100: collie: revert back to cfi_probe
ARM: 8080/1: mcpm.h: remove unused variable declaration
ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache
Will Deacon [Fri, 27 Jun 2014 16:01:47 +0000 (17:01 +0100)]
ARM: 8087/1: ptrace: reload syscall number after secure_computing() check
On the syscall tracing path, we call out to secure_computing() to allow
seccomp to check the syscall number being attempted. As part of this, a
SIGTRAP may be sent to the tracer and the syscall could be re-written by
a subsequent SET_SYSCALL ptrace request. Unfortunately, this new syscall
is ignored by the current code unless TIF_SYSCALL_TRACE is also set on
the current thread.
This patch slightly reworks the enter path of the syscall tracing code
so that we always reload the syscall number from
current_thread_info()->syscall after the potential ptrace traps.
Acked-by: Kees Cook <keescook@chromium.org> Tested-by: Kees Cook <keescook@chromium.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Laura Abbott [Fri, 27 Jun 2014 09:17:27 +0000 (10:17 +0100)]
ARM: 8086/1: Set memblock limit for nommu
Commit 1c2f87c (ARM: 8025/1: Get rid of meminfo) changed find_limits
to use memblock_get_current_limit for calculating the max_low pfn.
nommu targets never actually set a limit on memblock though which
means memblock_get_current_limit will just return the default
value. Set the memblock_limit to be the end of DDR to make sure
bounds are calculated correctly.
Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Unfortunately the detection was challenged on the defective unit used for tests:
one of the NOR chips did not respond to the CFI query.
Moreover that bad device needed extra delays on erase-suspend/resume cycles.
Tested personally on 3 different units and with feedback of two other users.
Signed-off-by: Andrea Adami <andrea.adami@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Thomas Petazzoni [Fri, 13 Jun 2014 09:58:38 +0000 (10:58 +0100)]
ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache
When a PL310 cache is used on a system that provides hardware
coherency, the outer cache sync operation is useless, and can be
skipped. Moreover, on some systems, it is harmful as it causes
deadlocks between the Marvell coherency mechanism, the Marvell PCIe
controller and the Cortex-A9.
To avoid this, this commit introduces a new Device Tree property
'arm,io-coherent' for the L2 cache controller node, valid only for the
PL310 cache. It identifies the usage of the PL310 cache in an I/O
coherent configuration. Internally, it makes the driver disable the
outer cache sync operation.
Note that technically speaking, a fully coherent system wouldn't
require any of the other .outer_cache operations. However, in
practice, when booting secondary CPUs, these are not yet coherent, and
therefore a set of cache maintenance operations are necessary at this
point. This explains why we keep the other .outer_cache operations and
only ->sync is disabled.
While in theory any write to a PL310 register could cause the
deadlock, in practice, disabling ->sync is sufficient to workaround
the deadlock, since the other cache maintenance operations are only
used in very specific situations.
Contrary to previous versions of this patch, this new version does not
simply NULL-ify the ->sync member, because the l2c_init_data
structures are now 'const' and therefore cannot be modified, which is
a good thing. Therefore, this patch introduces a separate
l2c_init_data instance, called of_l2c310_coherent_data.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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