Wayne Zou [Mon, 7 May 2012 04:47:30 +0000 (12:47 +0800)]
ENGR00180497 FB: Fix a bug: 'fb_set_par error, -22' when video playback on lvds
Change bg_id/fg_id variable to char array variable, and
avoid change the constant string in .rodata section.
[MX6Q SMD]fb: 'fb_set_par error, -22' prompted when mplay a video to lvds
/mnt/nfs/util/mplayer /mnt/nfs/test_stream/video/Mpeg4_SP1_1280x720_30fps.mp4
Before video playback finish, fb error message shows:
ENGR00181068: MX6 Source IPU_HSP and AXI clocks from 540M PFD.
IPU_HSP clocks should NOT be sourced from MMDC clock since the
MMDC clock can be scaled.
Move the IPU_HSP clock to be sourced from PLL3_PFD_540M instead.
Also don't source AXI_CLK from periph_clk as this domain is
scaled between 528MHz, 400MHz and 24MHz. Move AXI_CLK
clock to be sourced from PLL3_PFD_540M too.
When the system needs to enter low power mode, AXI_CLK is switched
from PLL3_PFD_540M to periph_clk. And then switched back
when low power mode is exited.
The code will print a warning message if PLL3_PFD_540M is
relocked to a different frequency when IPU_HSP or axi_clk is
sourced from it.
Currently remove the support for 400Mhz DDR working point for
MX6Q since we can get IPU underruns during the DDR frequency
transitions.
The DDR freq change code needs to ensure that all bus clocks
donot exceed max frequency during the frequency transition.
Chen Liangjun [Fri, 4 May 2012 09:49:51 +0000 (17:49 +0800)]
ENGR00181697 HDMI: fix ahb bus error bug
In ARIK, to prevent noise cause by false triggered burst, we reduce
the incr type to 4. and the change may cause bus_error because a
burst may unexpectly stop and thus an AHB bus error happens.
Reset HDMI Audio FIFO state to prevent AHB bus error. Signed-off-by: Chen Liangjun <b36089@freescale.com>
Robin Gong [Wed, 2 May 2012 07:36:49 +0000 (15:36 +0800)]
ENGR00181348-2 :sabresd pfuze support cpu internal LDO bypass
1. need add flag to let cpu freq driver know pfuze regulator is ok or not
,so that cpu freq driver can directly used, otherwise cpu freq should use
raw i2c write/read interface.
2. fix one build warning Signed-off-by: Robin Gong <B38343@freescale.com>
Robin Gong [Thu, 3 May 2012 10:11:06 +0000 (18:11 +0800)]
ENGR00181348-1 :sabresd pfuze support cpu internal LDO bypass
VDDCORE output directly from pfuze not internal anatop regulator,VDDCORE can
be adjust by pfuze regulator with deifferent cpu frequency, these patch should
be used with u-boot related patch, because LDO bypass is set on u-boot. u-boot
and kernel can be configured by CONFIG_MX6_INTER_LDO_BYPASS, by default it is
disabled, can be used on RevC. These code is put in arch/arm. Signed-off-by: Robin Gong <B38343@freescale.com>
Yuxi Sun [Wed, 2 May 2012 07:13:43 +0000 (15:13 +0800)]
ENGR00180530 ov5640 mipi: Add gain calculation and stream on/off in setting
Using steam on/off to prevent sensor from no frame come out sometimes,
and gain calculation is used to help conquer green color when take picture
at QSXGA.
Also add QCIF resolution for 15/30 fps in this patch.
Colin Cross [Fri, 3 Sep 2010 19:41:21 +0000 (12:41 -0700)]
mmc_block: Allow more than 8 partitions per card
Set the GENHD_FL_EXT_DEVT flag, which will allocate minor numbers
in major 259 for partitions past disk->minors.
Also remove the use of disk_devt to determine devidx from md->disk.
md->disk->first_minor is always initialized from devidx and can
always be used to recover it.
Liu Ying [Sat, 28 Apr 2012 05:24:45 +0000 (13:24 +0800)]
ENGR00181194 IPUv3:Correct pixel clock definition and register
MX6Q has 2 IPUs, each IPU has 2 DIs, so there are totally 4
different pixel clocks. This patch adds maximal pixel clock
number from 2 to 4. Also, the patch fixes potential build
warning caused by the overflow on ipu_lookups structure in case
MXC_IPU_MAX_NUM is 1.
Steve Cornelius [Fri, 20 Apr 2012 00:26:40 +0000 (17:26 -0700)]
ENGR00180943-14: Update internal definition of hardware link table list
Update internal definition of hardware link table list such that it can
work properly on both big and little endian 32-bit configurations. This
required pointer resizing, reserved-field initialization, and the
combination of both buffer-pool ID and offset fields into a common
32-bit value that can burst-read correctly.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Wed, 18 Apr 2012 22:09:09 +0000 (15:09 -0700)]
ENGR00180943-13: Extend for ARM/iMX6 compatibility
Extend for ARM/iMX6 compatibility, including:
- Cache coherence for all streaming buffer mappings
- Initialization from non-OF-dependent lower-level drivers
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Wed, 18 Apr 2012 21:38:50 +0000 (14:38 -0700)]
ENGR00180943-12: Extend to include support for ARM targets on iMX6 platforms
Extend to include support for ARM targets on iMX6 platforms, including:
- platform property detection when OF device properties unavailable
- ring entry direction clarification for DMA API access
- cache coherence for rings
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Add non-device-tree platform property detection for driver startup and
initialization for iMX6 family, including clock control, job ring
detection and initialization, and interrupt mapping.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Adrian Alonso [Wed, 25 Apr 2012 23:05:44 +0000 (18:05 -0500)]
ENGR00180236-2: spdif clk usecount is 1 when not in use
* Move spdif_core_clk enable from spdif_probe to spdif_startup
function in order to avoid initializing the core clock
when module is not in use.
* At spdif_shutdown disable spdif core_clk.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
ENGR00180882- MX6DL Add bus frequency scaling support.
Added support for changing DDR frequency on MX6DL.
During system IDLE, DDR freq can drop down to 24MHz
if none of the devices that need high AHB frequency
are active.
Changed the DDR code to handle both MX6Q and MX6DL
DDR and IOMUX settings.
Fixed bug associated incorrect IRAM memory allocation
used to store DDR and IOMUX data.
ENGR00180185: MX6-Add support for low power audio playback
The DDR frequency needs to be at 50MHz for low power audio
playback. So added a new low power mode for audio.
Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this
mode.
This patch postpones pixel clock and its parent clock(if
the parent clock usecount is 1) disabling time point
until DC/DP/DI enable bits are cleared in IPU_CONF
register to prevent LVDS display channel starvation for
some special LVDS display video mode.
Alan Tull [Wed, 18 Apr 2012 16:40:08 +0000 (11:40 -0500)]
ENGR00180350-2 HDMI set infoframe information
Get speaker allocation data block information from the EDID.
Translate the EDID speaker allocation to audio infoframe
speaker allocation (different bit mapping) given the number
of channels of audio being played.
Set channel count information in HDMI_FC_AUDICONF0.
Set speaker allocation information in HDMI_FC_AUDICONF2.
From CEA-861-D spec:
NOTE—HDMI requires the CT, SS and SF fields to be set to 0 (Refer
to Stream Header) as these items are carried in the audio stream.
Alan Tull [Wed, 18 Apr 2012 16:40:08 +0000 (11:40 -0500)]
ENGR00180350-1 HDMI set infoframe information
Get speaker allocation data block information from the EDID.
Translate the EDID speaker allocation to audio infoframe
speaker allocation (different bit mapping) given the number
of channels of audio being played.
Set channel count information in HDMI_FC_AUDICONF0.
Set speaker allocation information in HDMI_FC_AUDICONF2.
From CEA-861-D spec:
NOTE—HDMI requires the CT, SS and SF fields to be set to 0 (Refer
to Stream Header) as these items are carried in the audio stream.
Jason Liu [Wed, 11 Apr 2012 05:21:15 +0000 (13:21 +0800)]
ENGR00180636: tty/imx: lock check while handle sysrq message
Since the port->lock has already been hold when enter rx_interrupt,
and thus hold it on during handle_sysrq. We need check whether the
current console_write is for the sysrq message output or not and use
the correct lock mechanism.
Wayne Zou [Tue, 24 Apr 2012 00:28:05 +0000 (08:28 +0800)]
ENGR00180618 VDOA: Add vdoa_iram cmdline options and reduce used IRAM size
Add vdoa_iram command line options and reduce used IRAM size
by default to 72KBytes. So by default it only support
partially interleaved 4:2:0 output format.
- Add NAPI methods.
NAPI can improve the performance of high-speed networking,
which can reduce the cpu loading of interrupt generate and
drop packets.
- Enet RX FIFO overruns number has been reduced by NAPI method.
For the standby mode, we force SOC enter STOP mode
and drop the VDDARM_IN and VDDSOC_IN to 0.9V, we need
to disable L1 and L2 cache and invalidate L1 cache when
system resume, as the L1 cache memory's power is dropped
during standby, need to do the invalidation before re-enable
it.
Terry Lv [Mon, 16 Apr 2012 09:44:12 +0000 (17:44 +0800)]
ENGR00179722: MLB: set correct mlb sys clock in mx6dl
In Rigel validatioin, the MLB sys_clock isn't using the right frequency
after boot.
In arik, the register CBCMR controls gpu2d clock, not mlb clock, mlb is
sourced from axi_clock.
But In rigel, the axi clock is lower than in mx6q, so mlb need to find a
new clock root. The gpu2d clock is then root of mlb clock in rigel.
Thus we need to add setting to support this change.
ENGR00172292 usb otg: enable dtds postpone free on mx6
We found this bug occurs again on mx6 when running
CTS with ADB over USB. The system will hang without
any log, and screen a little mess.
It's proved to be a known USB IP issue: USB controller
may access a wrong address for the dTD and then hang.
Re enable this workaround to avoid any system unstability.
Jason Liu [Tue, 17 Apr 2012 11:08:00 +0000 (19:08 +0800)]
ENGR00179851: i.mx6dl: map the MEM mode to STANDBY mode
Due to i.mx6dl TO1.0(TKT094231), Suspend/resume cannot work
stable under deep sleep mode(Dormant, MEM MODE) thus we need
map the MEM mode to STANBY mode(ARM will not power off), this
issue will be fixed on TO1.1
Jason Liu [Tue, 17 Apr 2012 10:53:53 +0000 (18:53 +0800)]
ENGR00179782: i.mx6: consolidate mx6q/dl_revision() support
The idea is to get the soc silicon revision from DIGPROG register Of
ANATOP(USB_ANALOG_DIGPROG), which will make kernel code independent
with bootloader which need pass the system_rev by ATAG.
This patch also will print the chip name and revision when kernel boot
up since this information is important for customer to know.
Liu Ying [Mon, 16 Apr 2012 04:40:37 +0000 (12:40 +0800)]
ENGR00179685 MX6 clock:Cleanup LDB DI parent clock
According to ticket TKT071080, 0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1.
However, MX6DL uses mmdc_ch1 as LDB DI parent clock.
This patch corrects the LDB DI parent clock setting.
ENGR00179696 MX6Q/UART : fix the wrong DMA tranfer direction.
The current SDMA use the new DMA tranfer direction. But the UART still
uses the old. This cause the RX failed.
So use the new DMA transfer direction for UART.
Tony LIU [Mon, 16 Apr 2012 07:47:23 +0000 (15:47 +0800)]
ENGR00179679 Fix usb gadget suspend issue connected to usb charger
- the root cause of this issue is during resume process, USB clock
is not turned on for this USB charger case so that the second
suspend is processed without USB clock, it cause system hang
- in udc resume process, at this situation, we should exit low
power mode to enable the b session valid intrrupt to close the
usb clock when detach from usb charger
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
Liu Ying [Fri, 13 Apr 2012 10:10:14 +0000 (18:10 +0800)]
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
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