Xinyu Chen [Wed, 7 Mar 2012 02:17:21 +0000 (10:17 +0800)]
ENGR00176278 mx6: make local timer work with WAIT mode
As mx6q soc use one clock to provide for cpu and local timer,
the local timers will be stopped when enter wait mode.
This causes system hang when enter wait mode with local timer
enabled. So we should switch the clock event to GPT
broadcast clock event before entering wait mode, and disable
local timers. Todo this, following changes made:
* In arch_idle(), we check if the GPT broadcast clock
event is switched to one shot mode. If the kernel clocksource
is switched from jiffies one to GPT, then we can use GPT
as broadcast event. And switch from local timer to GPT broadcast
event before entering mx6q_wait. Otherwise, kernel will hange
if the SW jiffies clock source is used.
We call clockevents_notify to switch clock source.
* Remove the enable_wait_mode check in local timer setup.
* Always return 0 in GPT v2 timer's set_next_event routing.
All the GPTs are running in free run mode as what driver did.
So we should allow the GPT CNT register roll over to 0 when it
reaches 0xFFFFFFFF. And the next event written to compare register
can less than the current value in CNT.
If we refused to do roll over settings, the kernel will continues
to set_next_event to GPT when the next event is far away and
we return negative value. This is happend when one CPU is in idle
and no timewheel is being expired in short time.
Loren Huang [Fri, 11 May 2012 02:20:56 +0000 (10:20 +0800)]
ENGR00209022 Update gpu clock management code
-This patch from vivante.They need to bypass the
reference count in clock management code as they
may touch clock while they just want to change
power state.
Huang Shijie [Wed, 9 May 2012 06:00:57 +0000 (14:00 +0800)]
ENGR00182346-2 serial: unregister the console when the console is released
The old code does not unregister the console mxc_early_uart_console when
it is disabled. This may causes the global console `console_drivers` still
pointes an invalid console mxc_early_uart_console. A hung will be observed
in this situation.
These methods are invoked if the iMX uart is used in conjuction with kgdb during
early boot. In order to access the UART without the interrupts, the kernel uses
the basic polling methods for IO with the device. With these methods
implemented, it is now possible to enable kgdb during early boot over serial.
Now the purpose of cpu_active is mostly with bringing down a cpu, where
we mark it !active to avoid the load-balancer from moving tasks to it
while we tear down the cpu. This is required because we only update the
sched_domain tree after we brought the cpu-down. And this is needed so
that some tasks can still run while we bring it down, we just don't want
new tasks to appear.
On cpu-up however the sched_domain tree doesn't yet include the new cpu,
so its invisible to the load-balancer, regardless of the active state.
So instead of setting the active state after we boot the new cpu (and
consequently having to wait for it before enabling interrupts) set the
cpu active before we set it online and avoid the whole mess.
Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1323965362.18942.71.camel@twins Signed-off-by: Ingo Molnar <mingo@elte.hu>
Russell King [Thu, 19 Jan 2012 15:20:58 +0000 (15:20 +0000)]
ARM: fix rcu stalls on SMP platforms
We can stall RCU processing on SMP platforms if a CPU sits in its idle
loop for a long time. This happens because we don't call irq_enter()
and irq_exit() around generic_smp_call_function_interrupt() and
friends. Add the necessary calls, and remove the one from within
ipi_timer(), so that they're all in a common place.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Thomas Gleixner [Sat, 15 Oct 2011 00:22:43 +0000 (17:22 -0700)]
ARM: smpboot: Enable irqs on secondary CPU after marking it online/active
Patch is the last version from tglx on Oct 7.
Discussion is at: http://comments.gmane.org/gmane.linux.ports.arm.kernel/131919
The original commit message for the first patch version:
Frank Rowand reported:
I have a consistent (every boot) hang on boot with the RT patches.
With a few hacks to get console output, I get:
rcu_preempt_state detected stalls on CPUs/tasks
I have also replicated the problem on the ARM RealView (in tree) and
without the RT patches.
The problem ended up being caused by the allowed cpus mask being set
to all possible cpus for the ksoftirqd on the secondary processors.
So the RCU softirq was never executing on the secondary cpu.
The problem was that ksoftirqd was woken on the secondary processors before
the secondary processors were online. This led to allowed cpus being set
to all cpus.
wake_up_process()
try_to_wake_up()
select_task_rq()
if (... || !cpu_online(cpu))
select_fallback_rq(task_cpu(p), p)
...
/* No more Mr. Nice Guy. */
dest_cpu = cpuset_cpus_allowed_fallback(p)
do_set_cpus_allowed(p, cpu_possible_mask)
# Thus ksoftirqd can now run on any cpu...
</report>
The reason is that the ARM SMP boot code for the secondary CPUs enables
interrupts before the newly brought up CPU is marked online and
active.
That causes a wakeup of ksoftirqd or a wakeup of any other kernel
thread which is affine to the brought up CPU break that threads
affinity and therefor being scheduled on already online CPUs.
This problem has been observed on x86 before and the only solution is
to mark the CPU online and wait for the CPU active bit before the
point where interrupts are enabled.
Anson Huang [Tue, 8 May 2012 07:10:16 +0000 (15:10 +0800)]
ENGR00182243 [MX6]Fix suspend/resume issue
When there is pending wake up source before SOC enter DSM,
we should restore DDR IO and enable cache then return. Previous
code break r2 register which keep the iram stack addr, will
lead to DDR IO restore fail, need to avoid it.
Ryan QIAN [Mon, 7 May 2012 05:54:04 +0000 (13:54 +0800)]
ENGR00182054: [MX6]: always_present flag will't work as designed at some cond
As designed, when 'always_present' is set, it is assumed that cd_gpio should
be not set, and gpio_get_value(boarddata->cd_gpio) should return 0. But it is
not sure that the return value of gpio_get_value(0) is 0.
- check always_present first
- remove ESDHC_FLAG_GPIO_FOR_CD_WP flag if always_present is set.
Wayne Zou [Mon, 7 May 2012 04:47:30 +0000 (12:47 +0800)]
ENGR00180497 FB: Fix a bug: 'fb_set_par error, -22' when video playback on lvds
Change bg_id/fg_id variable to char array variable, and
avoid change the constant string in .rodata section.
[MX6Q SMD]fb: 'fb_set_par error, -22' prompted when mplay a video to lvds
/mnt/nfs/util/mplayer /mnt/nfs/test_stream/video/Mpeg4_SP1_1280x720_30fps.mp4
Before video playback finish, fb error message shows:
ENGR00181068: MX6 Source IPU_HSP and AXI clocks from 540M PFD.
IPU_HSP clocks should NOT be sourced from MMDC clock since the
MMDC clock can be scaled.
Move the IPU_HSP clock to be sourced from PLL3_PFD_540M instead.
Also don't source AXI_CLK from periph_clk as this domain is
scaled between 528MHz, 400MHz and 24MHz. Move AXI_CLK
clock to be sourced from PLL3_PFD_540M too.
When the system needs to enter low power mode, AXI_CLK is switched
from PLL3_PFD_540M to periph_clk. And then switched back
when low power mode is exited.
The code will print a warning message if PLL3_PFD_540M is
relocked to a different frequency when IPU_HSP or axi_clk is
sourced from it.
Currently remove the support for 400Mhz DDR working point for
MX6Q since we can get IPU underruns during the DDR frequency
transitions.
The DDR freq change code needs to ensure that all bus clocks
donot exceed max frequency during the frequency transition.
Chen Liangjun [Fri, 4 May 2012 09:49:51 +0000 (17:49 +0800)]
ENGR00181697 HDMI: fix ahb bus error bug
In ARIK, to prevent noise cause by false triggered burst, we reduce
the incr type to 4. and the change may cause bus_error because a
burst may unexpectly stop and thus an AHB bus error happens.
Reset HDMI Audio FIFO state to prevent AHB bus error. Signed-off-by: Chen Liangjun <b36089@freescale.com>
Robin Gong [Wed, 2 May 2012 07:36:49 +0000 (15:36 +0800)]
ENGR00181348-2 :sabresd pfuze support cpu internal LDO bypass
1. need add flag to let cpu freq driver know pfuze regulator is ok or not
,so that cpu freq driver can directly used, otherwise cpu freq should use
raw i2c write/read interface.
2. fix one build warning Signed-off-by: Robin Gong <B38343@freescale.com>
Robin Gong [Thu, 3 May 2012 10:11:06 +0000 (18:11 +0800)]
ENGR00181348-1 :sabresd pfuze support cpu internal LDO bypass
VDDCORE output directly from pfuze not internal anatop regulator,VDDCORE can
be adjust by pfuze regulator with deifferent cpu frequency, these patch should
be used with u-boot related patch, because LDO bypass is set on u-boot. u-boot
and kernel can be configured by CONFIG_MX6_INTER_LDO_BYPASS, by default it is
disabled, can be used on RevC. These code is put in arch/arm. Signed-off-by: Robin Gong <B38343@freescale.com>
Yuxi Sun [Wed, 2 May 2012 07:13:43 +0000 (15:13 +0800)]
ENGR00180530 ov5640 mipi: Add gain calculation and stream on/off in setting
Using steam on/off to prevent sensor from no frame come out sometimes,
and gain calculation is used to help conquer green color when take picture
at QSXGA.
Also add QCIF resolution for 15/30 fps in this patch.
Colin Cross [Fri, 3 Sep 2010 19:41:21 +0000 (12:41 -0700)]
mmc_block: Allow more than 8 partitions per card
Set the GENHD_FL_EXT_DEVT flag, which will allocate minor numbers
in major 259 for partitions past disk->minors.
Also remove the use of disk_devt to determine devidx from md->disk.
md->disk->first_minor is always initialized from devidx and can
always be used to recover it.
Liu Ying [Sat, 28 Apr 2012 05:24:45 +0000 (13:24 +0800)]
ENGR00181194 IPUv3:Correct pixel clock definition and register
MX6Q has 2 IPUs, each IPU has 2 DIs, so there are totally 4
different pixel clocks. This patch adds maximal pixel clock
number from 2 to 4. Also, the patch fixes potential build
warning caused by the overflow on ipu_lookups structure in case
MXC_IPU_MAX_NUM is 1.
Steve Cornelius [Fri, 20 Apr 2012 00:26:40 +0000 (17:26 -0700)]
ENGR00180943-14: Update internal definition of hardware link table list
Update internal definition of hardware link table list such that it can
work properly on both big and little endian 32-bit configurations. This
required pointer resizing, reserved-field initialization, and the
combination of both buffer-pool ID and offset fields into a common
32-bit value that can burst-read correctly.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Wed, 18 Apr 2012 22:09:09 +0000 (15:09 -0700)]
ENGR00180943-13: Extend for ARM/iMX6 compatibility
Extend for ARM/iMX6 compatibility, including:
- Cache coherence for all streaming buffer mappings
- Initialization from non-OF-dependent lower-level drivers
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Steve Cornelius [Wed, 18 Apr 2012 21:38:50 +0000 (14:38 -0700)]
ENGR00180943-12: Extend to include support for ARM targets on iMX6 platforms
Extend to include support for ARM targets on iMX6 platforms, including:
- platform property detection when OF device properties unavailable
- ring entry direction clarification for DMA API access
- cache coherence for rings
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Add non-device-tree platform property detection for driver startup and
initialization for iMX6 family, including clock control, job ring
detection and initialization, and interrupt mapping.
Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Adrian Alonso [Wed, 25 Apr 2012 23:05:44 +0000 (18:05 -0500)]
ENGR00180236-2: spdif clk usecount is 1 when not in use
* Move spdif_core_clk enable from spdif_probe to spdif_startup
function in order to avoid initializing the core clock
when module is not in use.
* At spdif_shutdown disable spdif core_clk.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
ENGR00180882- MX6DL Add bus frequency scaling support.
Added support for changing DDR frequency on MX6DL.
During system IDLE, DDR freq can drop down to 24MHz
if none of the devices that need high AHB frequency
are active.
Changed the DDR code to handle both MX6Q and MX6DL
DDR and IOMUX settings.
Fixed bug associated incorrect IRAM memory allocation
used to store DDR and IOMUX data.
ENGR00180185: MX6-Add support for low power audio playback
The DDR frequency needs to be at 50MHz for low power audio
playback. So added a new low power mode for audio.
Set the AHB to 25MHz, AXI to 50MHz and DDR to 50MHz in this
mode.
This patch postpones pixel clock and its parent clock(if
the parent clock usecount is 1) disabling time point
until DC/DP/DI enable bits are cleared in IPU_CONF
register to prevent LVDS display channel starvation for
some special LVDS display video mode.
Alan Tull [Wed, 18 Apr 2012 16:40:08 +0000 (11:40 -0500)]
ENGR00180350-2 HDMI set infoframe information
Get speaker allocation data block information from the EDID.
Translate the EDID speaker allocation to audio infoframe
speaker allocation (different bit mapping) given the number
of channels of audio being played.
Set channel count information in HDMI_FC_AUDICONF0.
Set speaker allocation information in HDMI_FC_AUDICONF2.
From CEA-861-D spec:
NOTE—HDMI requires the CT, SS and SF fields to be set to 0 (Refer
to Stream Header) as these items are carried in the audio stream.
Alan Tull [Wed, 18 Apr 2012 16:40:08 +0000 (11:40 -0500)]
ENGR00180350-1 HDMI set infoframe information
Get speaker allocation data block information from the EDID.
Translate the EDID speaker allocation to audio infoframe
speaker allocation (different bit mapping) given the number
of channels of audio being played.
Set channel count information in HDMI_FC_AUDICONF0.
Set speaker allocation information in HDMI_FC_AUDICONF2.
From CEA-861-D spec:
NOTE—HDMI requires the CT, SS and SF fields to be set to 0 (Refer
to Stream Header) as these items are carried in the audio stream.
Jason Liu [Wed, 11 Apr 2012 05:21:15 +0000 (13:21 +0800)]
ENGR00180636: tty/imx: lock check while handle sysrq message
Since the port->lock has already been hold when enter rx_interrupt,
and thus hold it on during handle_sysrq. We need check whether the
current console_write is for the sysrq message output or not and use
the correct lock mechanism.
Wayne Zou [Tue, 24 Apr 2012 00:28:05 +0000 (08:28 +0800)]
ENGR00180618 VDOA: Add vdoa_iram cmdline options and reduce used IRAM size
Add vdoa_iram command line options and reduce used IRAM size
by default to 72KBytes. So by default it only support
partially interleaved 4:2:0 output format.
- Add NAPI methods.
NAPI can improve the performance of high-speed networking,
which can reduce the cpu loading of interrupt generate and
drop packets.
- Enet RX FIFO overruns number has been reduced by NAPI method.
For the standby mode, we force SOC enter STOP mode
and drop the VDDARM_IN and VDDSOC_IN to 0.9V, we need
to disable L1 and L2 cache and invalidate L1 cache when
system resume, as the L1 cache memory's power is dropped
during standby, need to do the invalidation before re-enable
it.
Terry Lv [Mon, 16 Apr 2012 09:44:12 +0000 (17:44 +0800)]
ENGR00179722: MLB: set correct mlb sys clock in mx6dl
In Rigel validatioin, the MLB sys_clock isn't using the right frequency
after boot.
In arik, the register CBCMR controls gpu2d clock, not mlb clock, mlb is
sourced from axi_clock.
But In rigel, the axi clock is lower than in mx6q, so mlb need to find a
new clock root. The gpu2d clock is then root of mlb clock in rigel.
Thus we need to add setting to support this change.
projects / karo-tx-linux.git / log