Wolfram Sang [Wed, 21 Sep 2011 10:49:20 +0000 (12:49 +0200)]
gpio: move mpc8xxx/512x gpio driver to drivers/gpio
Move the driver to the place where it is expected to be nowadays. Also
rename its CONFIG-name to match the rest and adapt the defconfigs.
Finally, move selection of REQUIRE_GPIOLIB or WANTS_OPTIONAL_GPIOLIB to
the platforms, because this option is per-platform and not per-driver.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Anatolij Gustschin <agust@denx.de>
powerpc/5200: dts: digsy_mtc.dts: add timer0 and timer1 gpio properties
timer0 and timer1 pins are used as simple GPIO on this board.
Add gpio-controller and #gpio-cells properties to timer nodes
so that we can control gpio lines using available MPC52xx
GPT driver.
powerpc/5200: dts: digsy_mtc.dts: update to add can, pci, serial and spi
Add new nodes to describe more hardware the board is
equipped with:
- two can nodes for SJA1000 on localbus
- pci node to support Coral-PA graphics controller
- serial node for SC28L92 DUART on localbus
- spi node for MSP430 device
Stephen Warren [Tue, 20 Sep 2011 16:46:26 +0000 (10:46 -0600)]
arm/dt: Tegra: Add support-8bit to SDHCI nodes
For Seaboard's internal eMMC, this makes the difference between a
5.5MB/s and 10.2MB/s transfer rate. On Harmony, there wasn't any
measurable difference on my cheap/slow ~2MB/s card.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Nicolas Pitre [Wed, 3 Aug 2011 14:50:38 +0000 (15:50 +0100)]
ARM: mach-nuc93x: delete
This architecture received only generic maintenance since December 2009
when it was originally submitted, and no actual additional support since
then. It has no defconfig entry either, meaning that it was never built
by the ARM KAutobuild. Incidentally it currently doesn't build either
when CONFIG_MACH_NUC932EVB is selected which is the only possible config
choice.
This is therefore dead code and should be removed. If someone wants to
revive this code, it could be retrieved from the Git repository, and
ideally be merged in mach-w90x900/ instead.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Wan ZongShun <mcuos.com@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Linus Walleij [Fri, 12 Aug 2011 11:54:42 +0000 (13:54 +0200)]
ARM: mach-ux500: unlock I&D l2x0 caches before init
Apparently U8500 U-Boot versions may leave the l2x0 locked down
before executing the kernel. Make sure we unlock it before we
initialize the l2x0. This fixes a performance problem reported
by Jan Rinze.
The l2x0 core has been modified to unlock the l2x0 by default,
but it will not touch the locking registers if the l2x0 was
already enabled, as on the ux500, so we need this quirk to
make sure it is properly turned off.
Cc: stable@kernel.org Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Adrian Bunk <adrian.bunk@movial.com> Reported-by: Jan Rinze <janrinze@gmail.com> Tested-by: Robert Marklund <robert.marklund@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Brian King [Wed, 21 Sep 2011 13:51:11 +0000 (08:51 -0500)]
[SCSI] ipr: Stop reading adapter dump prematurely
When the ipr driver decides to dump the adapter, it changes the
sdt_state to GET_DUMP, then prepares the adapter so that the dump
can be read. However, if the ipr worker thread wakes up for some
reason before the driver has put the adapter in a state where it
can succesfully dump the adapter, the driver will start dumping
the adapter too early, which can potentially trigger a BUG check
in the pci config blocking API. Fix this by adding a new
sdt_state to differentiate between the ipr driver wanting to dump
the adapter in the near future and wanting to dump the adapter now.
Signed-off-by: Brian King <brking@linux.vnet.ibm.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
James Bottomley [Sun, 18 Sep 2011 14:56:20 +0000 (18:56 +0400)]
[SCSI] 3w-9xxx: fix iommu_iova leak
Following reports on the list, it looks like the 3e-9xxx driver will leak dma
mappings every time we get a transient queueing error back from the card.
This is because it maps the sg list in the routine that sends the command, but
doesn't unmap again in the transient failure path (even though the command is
sent back to the block layer). Fix by unmapping before returning the status.
Reported-by: Chris Boot <bootc@bootc.net> Tested-by: Chris Boot <bootc@bootc.net> Acked-by: Adam Radford <aradford@gmail.com> Cc: stable@kernel.org Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Finn Thain [Sun, 11 Sep 2011 09:57:51 +0000 (19:57 +1000)]
[SCSI] mac_esp: remove redundant mutual exclusion
Mutual exclusion is redundant here because all the paths in the call graph
leading to esp_driver_ops.send_dma_cmd() happen under spin_lock_irqsave/
spin_lock_irqrestore. Remove it.
Tested on a Mac Quadra 660av and a Mac LC 630.
Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
[SCSI] mpt2sas: Added NUNA IO support in driver which uses multi-reply queue support of the HBA
Support added for controllers capable of multi reply queues.
The following are the modifications to the driver to support NUMA.
1) Create the new structure adapter_reply_queue to contain the reply queue
info for every msix vector. This object will contain a
reply_post_host_index, reply_post_free for each instance, msix_index, among
other parameters. We will track all the reply queues on a link list called
ioc->reply_queue_list. Each reply queue is aligned with each IRQ, and is
passed to the interrupt via the bus_id parameter.
(2) The driver will figure out the msix_vector_count from the PCIe MSIX
capabilities register instead of the IOC Facts->MaxMSIxVectors. This is
because the firmware is not filling in this field until the driver has
already registered MSIX support.
(3) If the ioc_facts reports that the controller is MSIX compatible in the
capabilities, then the driver will request for multiple irqs. This count
is calculated based on the minimum between the online cpus available and
the ioc->msix_vector_count. This count is reported to firmware in the
ioc_init request.
(4) New routines were added _base_free_irq and _base_request_irq, so
registering and freeing msix vectors were done thru simple function API.
(5) The new routine _base_assign_reply_queues was added to align the msix
indexes across cpus. This will initialize the array called
ioc->cpu_msix_table. This array is looked up on every MPI request so the
MSIxIndex is set appropriately.
(6) A new shost sysfs attribute was added to report the reply_queue_count.
(7) User needs to set the affinity cpu mask, so the interrupts occur on the
same cpu that sent the original request.
Signed-off-by: Nagalakshmi Nandigama <nagalakshmi.nandigama@lsi.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Dan Williams [Fri, 2 Sep 2011 04:18:31 +0000 (21:18 -0700)]
[SCSI] isci: initial sgpio write support
Basic support to initialize the gpio unit, accept an incomming
SAS_GPIO_REG_TX_GP bitstream, and translate it to the ODx.n fields in
the hardware registers. If register indexes outside the supported range
are specified in the SMP frame we simply accept the write and return how
many registers (SFF-8485) were written (libsas reports this as residue
in the request).
Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Dan Williams [Fri, 2 Sep 2011 04:18:26 +0000 (21:18 -0700)]
[SCSI] isci: fix sgpio register definitions
output_data_select registers are off by one u32
delete the macros we will never use.
Reported-by: Artur Wojcik <artur.wojcik@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Dan Williams [Fri, 2 Sep 2011 04:18:20 +0000 (21:18 -0700)]
[SCSI] libsas: sgpio write support
Add SFF-8485 v0.7 / SAS-1 smp-write-gpio register support to libsas.
Defer SAS-2 support unless/until it defines an sgpio interface.
Minimum implementation needed to get the lights blinking.
try_test_sas_gpio_gp_bit() provides a common method to parse the
incoming write data (raw bitstream), and the to_sas_gpio_gp_bit() helper
routine can be used as a basis for the set/clear operations for the
'read' implementation. Host implementations parse as many bits
(ODx.[012]) as are locally supported and report the number of registers
successfully written. If the submitted data overruns the internal
number of registers available report the write as a success with the
number of bytes remaining reported in ->resid_len.
Example (assuming an active backplane) set the "identify" pattern for
the first 21 devices:
Michal Malý [Sat, 10 Sep 2011 19:28:23 +0000 (21:28 +0200)]
HID: "hid-logitech" driver with Logitech Driving Force GT
There's been a small oversight when adding support for Logitech Driving Force
GT. Entry in hid-core was missing so the generic driver instead of hid-logitech
was being used.
Signed-off-by: Michal Malý <madcatxster@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
The root cause was an EEH error, which sent us down the offload_close path in
the cxgb3 driver, which in turn sets cdev->l2opt to NULL, without regard for
upper layer driver (like the cxgbi drivers) which might have execution contexts
in the middle of its use. The result is the oops above, when t3_l2t_get attempts
to dereference L2DATA(cdev)->nentries in arp_hash right after the EEH error handler sets it to NULL.
The fix is to prevent the setting of the NULL pointer until after there are no
further users of it. The t3cdev->l2opt pointer is now converted to be an rcu
pointer and the L2DATA macro is now called under the protection of the
rcu_read_lock(). When the EEH error path:
t3_adapter_error->offload_close->cxgb3_offload_deactivate
Is exectured, setting of that l2opt pointer to NULL, is now gated on an rcu
quiescence point, preventing, allowing L2DATA callers to safely check for a NULL
pointer without concern that the underlying data will be freeded before the
pointer is dereferenced.
This has been tested by the reporter and shown to fix the reproted oops
Note: I had attempted to post a fix for this bug previously. While it solved
the issue, James B. pointed out that it really didn't make much sense, and on
closer inspection I agree. Some internal structures to this affected pointer are
already refcounted and so all we should need to do is prevent the race that
arises between the reading of the affected pointer and its setting to NULL.
Signed-off-by: Neil Horman <nhorman@tuxdriver.com> Reviewed-by: Karen Xie <kxie@chelsio.com> Cc: stable@kernel.org Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Signed-off-by: Randy Dunlap <rdunlap@xenotime.net> Reviewed-by: Mike Christie <michaelc@cs.wisc.edu> Cc: stable@kernel.org Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Mark Salyzyn [Thu, 1 Sep 2011 13:11:17 +0000 (06:11 -0700)]
[SCSI] libsas: fix failure to revalidate domain for anything but the first expander child.
In an enclosure model where there are chaining expanders to a large body
of storage, it was discovered that libsas, responding to a broadcast
event change, would only revalidate the domain of first child expander
in the list.
The issue is that the pointer value to the discovered source device was
used to break out of the loop, rather than the content of the pointer.
This still remains non-compliant as the revalidate domain code is
supposed to loop through all child expanders, and not stop at the first
one it finds that reports a change count. However, the design of this
routine does not allow multiple device discoveries and that would be a
more complicated set of patches reserved for another day. We are fixing
the glaring bug rather than refactoring the code.
Signed-off-by: Mark Salyzyn <msalyzyn@us.xyratex.com> Cc: stable@kernel.org Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Since commit [c58543c8: genirq: Run irq handlers with interrupts disabled],
we run all interrupt handlers with interrupts disabled
and we even check and yell when an interrupt handler
returns with interrupts enabled (see commit [b738a50a:
genirq: Warn when handler enables interrupts]).
hwmon: Add unspecified temperature thresholds to sysfs ABI
Some recent temperature sensor chips provide thresholds which are not associated
with lower or upper limits. The use of those thresholds is application specific.
Provide sysfs ABI attributes to support such thresholds.
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com> Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
hwmon: (coretemp) Add support for thermal threshold attributes
Add support for T0 and T1 temperature thresholds using the new sysfs ABI
attributes tempX_thresholdY and tempX_thresholdY_triggered.
This patch is based on commit c814a4c7c4aad795835583344353963a0a673eb0, which
was reverted. For details on the threshold registers, see IA Manual vol 3A,
which can be downloaded from here:
http://download.intel.com/design/processor/manuals/253668.pdf
Hans de Goede [Fri, 9 Sep 2011 10:12:35 +0000 (12:12 +0200)]
hwmon/f71882fg: Make the decision wether to register fan attr. per fan
Before this patch the f71882fg driver completely fails to initialize
on systems which have reserved settings in the pwm enable register, and
it disables all auto pwm sysfs attributes if any fan is controlled by
a digital sensor reading.
This patch changes the fail to initialize into don't register any attributes
for the fan for which there are reserved settings in the pwm enable register
and also makes the not registering of auto pwm sysfs attributes a per fan
thing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
hwmon: (pmbus) Always call _pmbus_read_byte in core driver
Always call _pmbus_read_byte() instead of pmbus_read_byte() in PMBus core
driver. With this change, device specific read functions can be implemented for
all registers.
Since the device specific read_byte function is now always called, we need to be
more careful with page validations. Only fail if the passed page number is larger
than 0, since -1 means "current page".
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com> Reviewed-by: Robert Coulson <robert.coulson@ericsson.com>