Anson Huang [Tue, 11 Nov 2014 02:13:58 +0000 (10:13 +0800)]
MLK-9823 arm: imx: correct L2 controller settings after resume
As we have specific tag and data latency settings on our platforms,
so we have to restore these settings after resume with L2 controller
power gated. Otherwise, system perpormance will be impacted a lot:
dd read test(dd if=/dev/mmcblk2 of=/dev/null bs=1M count=2000) of SD
card would lower from 61.4MB/s to 57.7MB/s, ~6% drop.
Issue reproduce steps:
1. Boot up without HDMI cable plugin
2. Insert the HDMI cable.
3. echo mem > /sys/power/state , enter suspend,
4. resume it,
System can resume from suspend but display is blank.
Error log:
mxc_sdc_fb fb.31: Unable to allocate framebuffer memory
detected fb_set_par error, error code: -12
In mxc hdmi driver, if system bootup without hdmi cable plugin,
driver will create a default modelist.
In fbcon driver, array fb_display[] initialized when system bootup
and save current mode pointer that point to default modelist.
When hdmi cable is plugin the modelist will rebuild according edid
data, but the pointer of video mode in fb_display[] is not updated.
When system resume, fbcon will use the invalidate pointer to
configured framebuffer, framebuffer will crash.
Add function fb_new_modelist() after modelist is rebuild to fix the
issue.
Anson Huang [Mon, 20 Jan 2014 11:30:09 +0000 (19:30 +0800)]
ENGR00295814 ARM: dts: imx6qdl: correct gpio key's active state
From schematic, below GPIO keys' active state is low, so we need
to set correct active state in dts.
i.MX6Q/DL-SABRESD board: power, vol+ and vol-.
i.MX6Q/DL-SABREAUTO board: home, back, prog, vol+ and vol-.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit f1319b3268db3e0e80d85ba9f4ae3b569b916dd4) Signed-off-by: Robin Gong <b38343@freescale.com>
ARM: imx: replace cpu type check with ddr type check
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3,
we used cpu type to decide how to do these settings in suspend
before which is NOT flexible, take i.MX6SL for example, although
it has LPDDR2 on EVK board, but users can also use DDR3 on other
boards, so it is better to read the DDR type from MMDC then decide
how to do related settings.
Sandor Yu [Fri, 7 Nov 2014 03:14:05 +0000 (11:14 +0800)]
MLK-9808 HDMI: EDID bug fixes / improvements
Changes in order of appearence:
- If an EDID extension block other than the known (CEA extension) is found
don't fail monitor detection completely, just proceed to the next block.
- If 4 or more extensions are present two problems arise:
- only 2 extensions will actually be read and
- parsing will read beyond the buffer.
Throw a BUG() and add a comment, don't have time for a rewrite right now.
- The EDID I2C read code has a 1 second timeout - per byte. With 128 bytes
per block this could take over 2 minutes. And we have indeed seen a very
long pause on Linux shutdown on rare occasions. At 100 kHz reading a byte
takes 0.6 ms, reduce the timeout to 30 ms.
- Checking extblknum < 0 is pointless when its value was assigned from an
unsigned char.
- Some old monitors didn't set the 'number of EDID ext. blocks' field. 0xFF
means no extensions.
- Calling mxc_edid_parse_ext_blk() only makes sense if an ext. block was
actually read. Otherwise it's sure to fail, and monitor detection with it.
- As the 1st extension was parsed beforehand the following for loop must
start at 2, otherwise the 1st extension is parsed twice.
- Inside the read loop all bytes were written to tmpedid[1], It should
tmpedid[i].
- And then when parsing the read data they have to start at tmpedid[0],
not at tmpedid[EDID_LENGTH], which is beyond the buffer.
- Improved debugging a bit by inserting a message if reading fails and also
removing one that may be confused with another with the same text.
- If getting the EDID data fails we will retry once. But if the failure was
due to not being able to parse the data rather than a read error
re-reading will yield HDMI_EDID_SAME. The code will misinterpret that as
'no change, video modes already set up'. Instead continue with the status
code of the initial attempt.
- Before retrying wait 0.2 s, most likely reading initially failed because
the cable had not been fully inserted.
ENGR00323271-02 hdmi: Add mipi core clock to hdmi drivers
HDMI isfr clock source from video 27M clock.
There are one clock gate control of video27m_root in CCM,
ccm_video27m_root_cg = ((lpcg_mipi_core_cfg_clk_enable_clock_root
| lpcg_mipi_core_pll_refclk_enable_clock_root) | lpcg_vpu_rclk_enable_clock_root);
The video 27M clock depend on vpu clock or mipi core clock.
In mx6 chip, vpu can been disabled by fuse,
so for vpu disabled case, mipi core clock should enabled and make sure
27M clock on.
Add mipi core clock management in hdmi drivers to support vpu disabled
case.
Liu Ying [Wed, 5 Nov 2014 07:28:29 +0000 (15:28 +0800)]
MLK-8906 video: mxc: mipi dsi: Set panel vm back to var in .setup()
In order to prevent some critical framebuffer var entries(e.g.,
sync/vmode flags) from being changed, this patch sets the active
mipi dsi panel's video mode back to the framebuffer var.
ENGR00332861 ARM:imx6x: Fix build break caused by GPU driver.
The GPU driver fails to build when the kernel is not built in-place,
KBUILD_OUTPUT is set to point to some other directory.
This patch fixes this issue.
Loren Huang [Fri, 15 Aug 2014 06:05:05 +0000 (14:05 +0800)]
ENGR00327306 [#1325]Make 3dMinClock be changeable
-Add sys interface for changing 3DMinClock.
This feature is blocked by vivante kernel platform change.
Sys interface /sys/bus/platform/drivers/galcore/gpu3DMinclock
is used for configure this value.
It's important feature for thermal.
it is not complete in the original implementation to query virtual command buffer,
it is necessary to this fix to get the correct GPU virtual memory result.
also include virtual command buffer database for Vivante gcDB tool.
Fugang Duan [Tue, 4 Nov 2014 05:23:34 +0000 (13:23 +0800)]
MLK-9786 net: fec: Add busfreq support to the driver
Add request_bus_freq() and release_bus_freq() calls to the
various drivers to ensure that the DDR and AHB are the requested
frequency before the driver starts its task.
Bai Ping [Fri, 31 Oct 2014 08:28:03 +0000 (16:28 +0800)]
MLK-9777 cpufreq: imx6: fix the high bus count mismatch
Normally, the system is booting up with higher cpufreq. In the
cpufreq set_target_index we will release the high bus mode if
the target cpu frequency is the lowest. It will release the high
bus mode and dcrease the high_bus_count.This will lead to a wrong
release of high bus mode. So, in the cpufreq_init function, if the
original frequency is not the lowest, we need request high busfreq.
Bai Ping [Mon, 27 Oct 2014 06:28:08 +0000 (14:28 +0800)]
MLK-9721 arm: imx6: add busfreq support for imx6sl
Add busfreq node in the dtsi file and modified the source code
to support imx6sl to enter low busfreq mode.
As the clk tree of imx6sl on 3.14 branch different with imx6q,
imx6sx, etc. So the busfreq change flow need some additional
code. Especially, after change the bus frequency to 24MHz, the
clock parent-child relationship need one more step to update.
Before change to 24MHz low bus mode, the clock tree between the
OSC and MMDC as below:
So the parent of pll2_bypass clock need to be set to pll2_bypass_src after
entering 24MHz mode, and set to pll2 after exiting 24MHz to reflect the correct
parent-child relationship in kernel.
Changing dev_dbg to printk to ease the debug of busfreq driver, print the busfreq
change information as needed.
Fancy Fang [Mon, 20 Oct 2014 09:09:38 +0000 (17:09 +0800)]
MLK-6304 IPUv3 device: Enable IC task when cropping is needed.
For the case that, the input and output size are both 640x480,
but the video20's related framebuffer resolution is 1024x768,
so the output should be cropped. In this situation, the ipu
task should be set to IC_MODE to avoid 'IPU_CHECK_ERR_PROC_NO_NEED'
error reporting.
Luwei Zhou [Wed, 22 Oct 2014 06:32:56 +0000 (14:32 +0800)]
MLK-9716 net: fec: Fix the kernel panic issue on i.MX6SL-EVK board.
The i.MX6SL-EVK FEC IP doesn't support PTP feature. After adding
PPS support, irq handler will invoke fec_check_pps_status function.
We need to add a condition judge.
MLK-9685 ARM:imx6x:Ensure that the kernel can boot with "nosmp" in the command line
When nosmp is added to the command line, setup_max_cpus is set to 0
by the kernel. And this results in num_possible_cpus() returning 0 and the kernel
does not boot.
This patch ensures that at least one CPU's state is set to "possible" as part
of the boot process.
Anson Huang [Mon, 20 Oct 2014 08:16:20 +0000 (16:16 +0800)]
MLK-9708 arm: imx: add low power idle support for i.mx6sx
1. improve imx6q_set_int_mem_clk_lpm routine;
2. export rbc enable interface for cpuidle;
3. enable low power idle for i.MX6SX:
WFI -> first level idle;
WAIT mode -> second level idle;
Low power idle -> third level idle, only when system is in low bus mode.
In low powe idle mode, below operations will be done:
ARM power off;
AHB freq lower to 3MHz;
PERCLK freq lower to 6MHz;
MMDC freq lower to 1MHz;
Anatop will be put into low power mode, and regular band-gap will
be off and low power band-gap will be enabled instead.
Also, in low power idle mode, 24MHz XTAL power will be off and 24MHz clk
source will be switched to RC-OSC to save power, this feature is only
enabled on i.MX6SX TO1.2.
Luwei Zhou [Fri, 10 Oct 2014 05:15:30 +0000 (13:15 +0800)]
net: fec: ptp: Enable PPS output based on ptp clock
FEC ptp timer has 4 channel compare/trigger function. It can be used to
enable pps output.
The pulse would be ouput high exactly on N second. The pulse ouput high
on compare event mode is used to produce pulse per second. The pulse
width would be one cycle based on ptp timer clock source.Since 31-bit
ptp hardware timer is used, the timer will wrap more than 2 seconds. We
need to reload the compare compare event about every 1 second.
Signed-off-by: Luwei Zhou <b45643@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Richard Cochran [Thu, 20 Mar 2014 21:21:55 +0000 (22:21 +0100)]
ptp: drivers: set the number of programmable pins.
This patch updates the many PTP Hardware Clock drivers with the
newly introduced field that advertises the number of programmable
pins. Some of these devices do have programmable pins, but the
implementation will have to wait for follow on patches.
Signed-off-by: Richard Cochran <richardcochran@gmail.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Richard Cochran [Thu, 20 Mar 2014 21:21:52 +0000 (22:21 +0100)]
ptp: introduce programmable pins.
This patch adds a pair of new ioctls to the PTP Hardware Clock device
interface. Using the ioctls, user space programs can query each pin to
find out its current function and also reprogram a different function
if desired.
Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Luwei Zhou [Fri, 10 Oct 2014 05:15:29 +0000 (13:15 +0800)]
net: fec: ptp: Use hardware algorithm to adjust PTP counter.
The FEC IP supports hardware adjustment for ptp timer. Refer to the description of
ENET_ATCOR and ENET_ATINC registers in the spec about the hardware adjustment. This
patch uses hardware support to adjust the ptp offset and frequency on the slave side.
Signed-off-by: Luwei Zhou <b45643@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Fugang Duan <b38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Luwei Zhou [Fri, 10 Oct 2014 05:15:28 +0000 (13:15 +0800)]
net: fec: ptp: Use the 31-bit ptp timer.
When ptp switches from software adjustment to hardware ajustment, linux ptp can't converge.
It is caused by the IP limit. Hardware adjustment logcial have issue when ptp counter
runs over 0x80000000(31 bit counter). The internal IP reference manual already remove 32bit
free-running count support. This patch replace the 32-bit PTP timer with 31-bit.
Signed-off-by: Luwei Zhou <b45643@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Nimrod Andy [Mon, 13 Oct 2014 02:53:48 +0000 (10:53 +0800)]
net: fec: Fix sparse warnings with different lock contexts for basic block
reproduce:
make ARCH=arm C=1 2>fec.txt drivers/net/ethernet/freescale/fec_main.o
cat fec.txt
sparse warnings:
drivers/net/ethernet/freescale/fec_main.c:2916:12: warning: context imbalance
in 'fec_set_features' - different lock contexts for basic block
Christopher Li suggest to change as below:
if (need_lock) {
lock();
do_something_real();
unlock();
} else {
do_something_real();
}
Reported-by: Fabio Estevam <festevam@gmail.com> Suggested-by: Christopher Li <sparse@chrisli.org> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Shawn Guo [Fri, 23 May 2014 08:41:28 +0000 (16:41 +0800)]
pwm: imx: set can_sleep flag for imx_pwm
The .config() hook imx_pwm_config() calls clk APIs like clk_prepare()
and clk_get_rate(), which might sleep, so we need to set can_sleep flag
on pwm_chip.
Liu Ying [Wed, 28 May 2014 10:50:13 +0000 (18:50 +0800)]
pwm: imx: Avoid sample FIFO overflow for i.MX PWM version2
The i.MX PWM version2 is embedded in several i.MX SoCs, such as i.MX27,
i.MX51 and i.MX6SL. There is a 4-word (16 bit) sample FIFO in this IP.
Each FIFO slot determines the duty period of a PWM waveform in one full
cycle. The IP spec mentions that we should not write a fourth sample
because the FIFO will become full and triggers a FIFO write error (FWE)
which will prevent the PWM from starting once it is enabled. In order
to avoid any sample FIFO overflow issue, this patch clears all sample
FIFO by doing software reset in the configuration hook when the
controller is disabled or waits for a full PWM cycle to get a
relinquished FIFO slot when the controller is enabled and the FIFO is
fully loaded.
The FIFO overflow issue can be reproduced by the following commands on
the i.MX6SL EVK platform, assuming we use PWM2 for the debug LED which
is driven by the pin HSIC_STROBE and the maximal brightness is 255.
MLK-9704 videobuf-dma-contig: set vm_pgoff to be zero to pass the sanity check in vm_iomap_memory().
When user requests V4L2_MEMORY_MMAP type buffers, the videobuf-core
will assign the corresponding offset to the 'boff' field of the
videobuf_buffer for each requested buffer sequentially. Later, user
may call mmap() to map one or all of the buffers with the 'offset'
parameter which is equal to its 'boff' value. Obviously, the 'offset'
value is only used to find the matched buffer instead of to be the
real offset from the buffer's physical start address as used by
vm_iomap_memory(). So, in some case that if the offset is not zero,
vm_iomap_memory() will fail.
Bai Ping [Wed, 15 Oct 2014 01:04:02 +0000 (09:04 +0800)]
MLK-9693 cpufreq: imx: increase cpufreq during suspend/resume
During suspend/ressume, when cpufreq driver try to increase
Voltage/freq, it needs to control I2C/SPI to communicate with
external PMIC to adjust voltage, but these I2C/SPI devices may
be already suspended, to avoid such scenario, we adjust increase
cpufreq to highest setpoint before suspend.
As this pm notification's updating cpu policy may work together
with cpufreq governor, both of them may call set_target at same
time, so we need to add mutex lock to prevent this scenario,
otherwise, the clock use count will be wrong.
this patch is copyed from imx_3.10.y branch (commit: 6f015845f6f)
Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com>
Fugang Duan [Wed, 15 Oct 2014 01:36:40 +0000 (09:36 +0800)]
MLK-9694 ARM: imx6: init enet MAC address
Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.
When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAC address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.
Bai Ping [Tue, 14 Oct 2014 02:17:16 +0000 (10:17 +0800)]
MLK-9678 arm: imx6: switch to analog bypass before entering DSM
this patch implements the workaround for ERR005852:
ERR005852 Analog: Transition from Deep Sleep Mode to LDO Bypass
Mode may cause the slow response of the VDDARM_CAP output.
Normally, the VDDARM_CAP supply takes only approximately 40 us
to raise to the correct voltage when exiting from Deep Sleep(DSM)
mode, if the LDO is enabled. If the LDO bypass mode is selected,
the VDDARM_CAP supply voltage will drop to approximately 0V when
entering and when exiting from DSM,even though the VDDARM_IN
supply is already stable, the VDDARM_CAP supply will take about
2 ms to rise to the correct voltage.
software workaround:
if internal LDO bypass, switch to analog bypass mode(0x1E), prior
to entering DSM, and then, revert to the normal bypass mode, when
exiting from DSM.
Robin Gong [Thu, 3 Apr 2014 09:10:24 +0000 (17:10 +0800)]
ENGR00307017: input: keyboard: snvs_pwrkey: fix system crash sometimes during boot
If there is one ONOFF power key interrupt pending before RESET key pushed. system will
crash as below in the next boot cycle, because the pending interrupt will be serviced
after devm_request_irq while the driver probe has not finished and the drvdata is NULL.
So clear the meaningless irq status in the probe.
Anson Huang [Fri, 10 Oct 2014 02:34:39 +0000 (10:34 +0800)]
MLK-9669-5 arm: imx: enable busfreq for i.mx6
enable busfreq for i.mx6 SOCs, only support i.MX6Q/DL/SX
DDR3 platform, i.MX6SL and LPDDR2 will be enabled later.
As there are too many conflicts using cherry-pick, so these
files are copied from L3.10.y branch(b01578a8d466d7420cbc7cfabf984998e8e31657),
please check L3.10.y for history.
Anson Huang [Thu, 9 Oct 2014 10:04:39 +0000 (18:04 +0800)]
MLK-9669-2 arm: imx: fix the clock warning printed during ddr frequency change procedure.
Recent checks added to the clock code prints warning during ddr frequency change procedure.
Hence the clock rates printed by clk_summary after ddr freq change are incorrect.
This patch fixes the issue by:
1. Removing CLK_SET_RATE_GATE for ocram_clk since it has a busy bit to be checked when
the ocram_podf is changed.
Anson Huang [Thu, 9 Oct 2014 09:50:46 +0000 (17:50 +0800)]
MLK-9669-1 arm: imx: skip system bus related clks parent switch check
Those system bus related mux only can be switched by busfreq driver,
and in busfreq asm code, it already follow the flow that hardware design
require, so no need to do flow check for these clk mux:
i.MX6Q/DL: periph_clk2_sel and pre_periph_clk_sel;
i.MX6SL: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel
i.MX6SX: periph_clk2_sel, pre_periph_clk_sel,
periph2_clk2_sel and pre_periph2_clk_sel.
e-n-g-r 00298524-6 ARM: imx: enable suspend/resume for i.mx6sx
Enable suspend/resume feature for i.mx6sx 17x17 arm2 board,
for dsm mode, as we use dedicated ocram space for low
power function(start from 0x8f8000), but ROM code still
use previous ocram space(0x900000) for checking jump address,
so we need to enable ROMCP of data patch to workaround this
issue.
Signed-off-by: Bai Ping <b51503@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
Fugang Duan [Fri, 10 Oct 2014 09:02:39 +0000 (17:02 +0800)]
ENGR00301115 net: fec_ptp: fix convergence issue to support IXXAT and LinuxPTP stack
IEEE 1588 module has one hw issue in capturing the ATVR register. According
to the user manual it is:
ENET0->ATCR |= ENET_ATCR_CAPTURE_MASK;
while(ENET0->ATCR & ENET_ATCR_CAPTURE_MASK);
ts_counter_ns = ENET0->ATVR;
Incorrect behavior for ENET_ATCR[Capture and Restart Bits]. These bits will always
read a value zero. According to SPEC, when these bits are set to 1'b1, these should
hold value 1'b1 until the counter value is capture in the register clock domain.
Unfortunately there is a bug with the way the bit "ENET_ATCR_CAPTURE" clears.
So need something like:
ENET0->ATCR |= ENET_ATCR_CAPTURE_MASK;
wait();
ts_counter_ns = ENET0->ATVR;
The wait-time to be at least 6 clock cycle of the slower clock between the register
clock and the 1588 clock. The 1588 ts_clk is 25Mhz, register clock is 66Mhz, so the
wait-time must be greater than 240ns (40ns * 6). The workaround is that adding 1us
delay before read ATVR.
Fugang Duan [Fri, 10 Oct 2014 08:25:26 +0000 (16:25 +0800)]
ENGR00299323-10 net:fec: add enet AVB Ubuntu Gstreamer demo support
Support Gstreamer AVB demo support.
ring1 -> ClassA, ring2 -> ClassB, ring0 -> Best Effort
For QoS: ring1 > ring2 > ring0
For bandwidth reverse:
50% bandwidth -> ClassA
33% bandwidth -> ClassB
17% bandwidth -> Best effort queue
In general, ClassA run audio, ClassB run video.
Since AVB demo use big bandwidth streaming, video cost more than
33Mbps bandwidth, and with Qos limitation: ClassA >= ClassB > Best effort,
so we have to change ring2 bandwidth equal to ring1 bandwidth (50%).
After validate on FPGA, AVB demo can work fine for audio and video.
Fugang Duan [Mon, 4 Aug 2014 07:27:50 +0000 (15:27 +0800)]
ENGR00329822-04 tty: serial: imx: optimize the rx performance
Optimize the uart rx performance that use SDMA loop mode instead
of normal mode. After the changes, uart rx fifo overrun issue disappear
even if hw flow control is disabled.
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 3a3eadcc2ab02029236fd0a5ae1c4e9369781157)
Fugang Duan [Mon, 4 Aug 2014 05:24:08 +0000 (13:24 +0800)]
ENGR00329822-03 tty: serial: imx: separate DMA and flow control features
The current implenention is that DMA feature is dependent on hw flow
control feature. But Uart DMA feature has nothing related to flow
control feature, so separate them.
Fix loop mode issue that calling dmaengine_tx_status() can get
right state.residue value.
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 37e17f10b35c34317def08704e4b4edf5aa23894)
but same command on /dev/video17 as following works well
/unit_tests/mxc_v4l2_output.out -d /dev/video17 -iw 320 -ih 240 -f RGBP -ow 320 -oh 240 anyfile.rgb
"
The 'IPU_PIX_FMT_RGB666' should be marked as RGB colorspace to
avoid unnecessary ipu task submit which will be considered to
be a 'IPU_CHECK_ERR_PROC_NO_NEED' error by IPU driver.
Peng Fan [Fri, 26 Sep 2014 09:15:14 +0000 (17:15 +0800)]
MLK-9644 imx6:dtb: reserve 16KB for IRAM TLB
Reserve 16KB for IRAM TLB. Except mx6sx, all others use 0x900000 as
the IRAM TLB base addr. To mx6sx, 0x8f8000 is used for IRAM TLB base
addr. Actually, 16KB is reserved for IRAM TLB, but only upper 8KB
is used for kernel TLB, the lower 8KB is used for pm_info and OCRAM
code.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ping Bai <Ping.Bai@freescale.com>
Robby Cai [Fri, 15 Nov 2013 09:21:16 +0000 (17:21 +0800)]
ENGR00288196 ARM: dts: fix epdc and csi conflict on imx6sl evk
There is pinmux conflict for EPDC and I2C3 on imx6sl soc.
While on imx6sl evk board, the camera is attached on I2C3 bus, so the
EPDC function and CSI function can not be used at same time.
This patch removes the conflict in imx6sl-evk.dts file for EPDC function
and adds a new dts file for CSI function.
Fabio Estevam [Sat, 4 Oct 2014 16:40:01 +0000 (13:40 -0300)]
fec: Fix fec_enet_alloc_buffers() error path
When fec_enet_alloc_buffers() fails we should better undo the previous actions,
which consists of: disabling the FEC clocks and putting the FEC pins into
inactive state.
The error path for fec_enet_mii_probe() is kept unchanged.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/freescale/fec_main.c: In function 'fec_enet_rx_queue':
>> drivers/net/ethernet/freescale/fec_main.c:1470:3: error: implicit declaration of function 'prefetch' [-Werror=implicit-function-declaration]
prefetch(skb->data - NET_IP_ALIGN);
^
cc1: some warnings being treated as errors
missed included prefetch.h
Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
projects / karo-tx-linux.git / log