Ben Skeggs [Sun, 22 Nov 2015 19:24:32 +0000 (05:24 +1000)]
drm/nouveau/gr/gf100-: split out per-gpc address calculation macro
There's a few places where we need to access a GPC register from ucode,
but outside of the falcon's io address space. To do this we need to
calculate the offset based on which GPC we're executing on.
This used to be done manually, but we've since found a "base" offset
that can be added by the hardware. To use this, an extra bit needs to
be set in the register address, which is what this macro achieves.
There should be no functional change from this commit.
Ilia Mirkin [Sat, 31 Oct 2015 19:06:11 +0000 (15:06 -0400)]
drm/nouveau/pci: enable c800 magic for Medion Erazer X7827
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91557 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ilia Mirkin [Tue, 27 Oct 2015 21:39:49 +0000 (17:39 -0400)]
drm/nouveau/pci: enable c800 magic for Lenovo Y510P
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70354#c75 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Karol Herbst [Sun, 16 Aug 2015 08:19:25 +0000 (10:19 +0200)]
drm/nouveau/pll/gk104: fix PLL instability due to bad configuration with gddr5
This patch uses an approach closer to the nvidia driver to configure
both PLLs for high gddr5 memory clocks (usually above 2400MHz)
Previously nouveau used the one PLL as it was used for the lower clocks
and just adjusted the second PLL to get as close as possible to the
requested clock. This means for my card, that I got a 4050 MHz clock
although 4008 MHz was requested.
Now the driver iterates over a list of PLL configuration also used by
the nvidia driver and then adjust the second PLL to get near the
requested clock. Also it hold to some restriction I found while
analyzing the PLL configurations
This won't fix all gddr5 high clock issues itself, but it should be
fine on hybrid gpu systems as found on many laptops these days. Also
switching while normal desktop usage should be a lot more stable than
before.
v2: move the pll code into ramgk104
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Roy Spliet [Tue, 29 Sep 2015 23:23:50 +0000 (00:23 +0100)]
drm/nouveau/fb/ramnv50: Script changes for G94 and up
10053c is not even read on some cards, and I have no idea exactly what the
criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables
all features that are never used. The practical effect should be the same
as this implementation though.
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Pierre Moreau [Sat, 3 Oct 2015 19:35:16 +0000 (21:35 +0200)]
drm/nouveau/pci: Handle 5-bit and 8-bit tag field
If the hardware supports extended tag field (8-bit ones), then enable it.
This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).
In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.
Fixes: fdo#86537
v2: Restrict changes to chipsets >= 0x84
v3:
* Add nvkm_pci_mask to pci.h
* Mask bit 8 before setting it
v4:
* Rename `add` argument of nvkm_pci_mask to `value`
* Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
checks
v5:
* Rebase code on latest PCI structure
* Restore PCIe check
* Fix namings in nvkm_pci_mask
* Rephrase part of the commit message
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ilia Mirkin [Wed, 7 Oct 2015 22:39:32 +0000 (18:39 -0400)]
drm/nouveau/gr: document mp error 0x10
NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE,
which apparently happens when trying to use an atomic operation on
local or shared memory (instead of global memory).
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 1 Oct 2015 01:36:58 +0000 (11:36 +1000)]
drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by default
Was not able to obtain a trace of NVRM due to kernel version annoyances,
however, experimentally confirmed that the WAR we use on NV50/G8x boards
works here too.
Samuel Pitoiset [Thu, 24 Sep 2015 18:26:15 +0000 (20:26 +0200)]
drm/nouveau/ibus/gf100: increase wait timeout to avoid read faults
Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.
This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Martin Peres [Wed, 16 Sep 2015 19:45:33 +0000 (22:45 +0300)]
drm/nouveau/gm204/6: add voltage control using the new gk104 volt class
I got confirmation that we can read and change the voltage with the same code.
The divider is also computed correctly on the gm204 we got our hands on.
Thanks to Yoshimo on IRC for executing the tests on his gm204!
Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Martin Peres [Tue, 8 Sep 2015 22:34:33 +0000 (00:34 +0200)]
drm/nouveau/volt/gk104: add support for pwm and gpio modes
Most Keplers actually use the GPIO-based voltage management instead of the new
PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles
the case where no GPIOs exist.
All the Maxwells seem to use the PWM method though.
v2:
- Do not forget to commit the PWM configuration change!
Signed-off-by: Martin Peres <martin.peres@free.fr>
drm/nouveau/ttm: set the DMA mask for platform devices
So far the DMA mask was not set for platform devices, which limited them
to a 32-bit physical space. Allow dma_set_mask() to be called for
non-PCI devices, and also take the IOMMU bit into account since it could
restrict the physically addressable space.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
The Great Nouveau Refactoring Take II brought us a lot of goodness,
including acquire/release methods that are called before and after an
instobj is modified. These functions can be used as synchronization
points to manage CPU/GPU coherency if we modify an instobj using the
CPU.
This patch replaces the legacy and slow PRAMIN access for gk20a instmem
with CPU mappings and writes. A LRU list is used to unmap unused
mappings after a certain threshold (currently 1MB) of mapped instobjs is
reached. This allows mappings to be reused most of the time.
Accessing instobjs using the CPU requires to maintain the GPU L2 cache,
which we do in the acquire/release functions. This triggers a lot of L2
flushes/invalidates, but most of them are performed on an empty cache
(and thus return immediately), and overall context setup performance
greatly benefits from this (from 250ms to 160ms on Jetson TK1 for a
simple libdrm program).
Making L2 management more explicit should allow us to grab some more
performance in the future.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reintroduce macros allowing us to test a register against a certain
mask, since this is the most common usage pattern for the more generic
nvkm_xsec macros and makes the code more concise and readable.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ilia Mirkin [Tue, 20 Oct 2015 05:15:39 +0000 (01:15 -0400)]
drm/nouveau/gem: return only valid domain when there's only one
On nv50+, we restrict the valid domains to just the one where the buffer
was originally created. However after the buffer is evicted to system
memory, we might move it back to a different domain that was not
originally valid. When sharing the buffer and retrieving its GEM_INFO
data, we still want the domain that will be valid for this buffer in a
pushbuf, not the one where it currently happens to be.
This resolves fdo#92504 and several others. These are due to suspend
evicting all buffers, making it more likely that they temporarily end up
in the wrong place.
Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92504 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Dave Airlie [Thu, 29 Oct 2015 23:49:06 +0000 (09:49 +1000)]
Merge tag 'topic/drm-misc-2015-10-22' of git://anongit.freedesktop.org/drm-intel into drm-next
Few more drm-misc stragglers for 4.4. Big thing is the generic probe for
imx/rockchip/armada (but the variant for msm/rpi/exynos is still missing).
Also the hdmi clocking fixes from Ville which was a lot of confusion about
which tree it should be applied to ;-)
* tag 'topic/drm-misc-2015-10-22' of git://anongit.freedesktop.org/drm-intel:
drm: correctly check failed allocation
vga_switcheroo: Constify vga_switcheroo_handler
drm/armada: Convert the probe function to the generic drm_of_component_probe()
drm/rockchip: Convert the probe function to the generic drm_of_component_probe()
drm/imx: Convert the probe function to the generic drm_of_component_probe()
drm: Introduce generic probe function for component based masters.
drm/edid: Round to closest when computing the CEA/HDMI alternate clock
drm/edid: Fix up clock for CEA/HDMI modes specified via detailed timings
Dave Airlie [Thu, 29 Oct 2015 23:48:28 +0000 (09:48 +1000)]
Merge branch 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux into drm-next
More amdgpu and radeon stuff for drm-next. Stoney support is the big change.
The rest is just bug fixes and code cleanups. The Stoney stuff is pretty
low impact with respect to existing chips.
* 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux:
drm/amdgpu: change VM size default to 64GB
drm/amdgpu: add Stoney pci ids
drm/amdgpu: update the core VI support for Stoney
drm/amdgpu: add VCE support for Stoney (v2)
drm/amdgpu: add UVD support for Stoney
drm/amdgpu: add GFX support for Stoney (v2)
drm/amdgpu: add SDMA support for Stoney (v2)
drm/amdgpu: add DCE support for Stoney
drm/amdgpu: Update SMC/DPM for Stoney
drm/amdgpu: add GMC support for Stoney
drm/amdgpu: add Stoney chip family
drm/amdgpu: fix the broken vm->mutex V2
drm/amdgpu: remove the unnecessary parameter adev for amdgpu_fence_wait_any()
drm/amdgpu: remove the exclusive lock
drm/amdgpu: remove old lockup detection infrastructure
drm: fix trivial typos
drm/amdgpu/dce: simplify suspend/resume
drm/amdgpu/gfx8: set TC_WB_ACTION_EN in RELEASE_MEM packet
drm/radeon: Use rdev->gem.mutex to protect hyperz/cmask owners
Dave Airlie [Thu, 29 Oct 2015 23:45:33 +0000 (09:45 +1000)]
Merge tag 'drm-intel-next-fixes-2015-10-22' of git://anongit.freedesktop.org/drm-intel into drm-next
Bunch of -fixes for 4.4. Well not just, I've left the mmio/register work
from Ville in here since it's low-risk but lots of churn all over.
* tag 'drm-intel-next-fixes-2015-10-22' of git://anongit.freedesktop.org/drm-intel: (23 commits)
drm/i915: Use round to closest when computing the CEA 1.001 pixel clocks
drm/i915: Kill the leftover RMW from ivb_sprite_disable()
drm/i915: restore ggtt double-bind avoidance
drm/i915/skl: Enable pipe gamma for sprite planes.
drm/i915/skl+: Enable pipe CSC on cursor planes. (v2)
MAINTAINERS: add link to the Intel Graphics for Linux web site
drm/i915: Move skl/bxt gt specific workarounds to ring init
drm/i915: Drop i915_gem_obj_is_pinned() from set-cache-level
drm/i915: revert a few more watermark commits
drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE
drm/i915: Clean up LVDS register handling
drm/i915: Throw out some useless variables
drm/i915: Parametrize and fix SWF registers
drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.
drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function
drm/i915: Fix a few bad hex numbers in register defines
drm/i915: Protect register macro arguments
drm/i915: Include gpio_mmio_base in GMBUS reg defines
drm/i915: Parametrize HSW video DIP data registers
drm/i915: Eliminate weird parameter inversion from BXT PPS registers
...
Dave Airlie [Fri, 23 Oct 2015 01:54:03 +0000 (11:54 +1000)]
Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next
A bit smaller pull this time. Few minor things, plus initial support
for msm8996 (snapdragon 820).. Sorry, a bit latish, was hoping to get
some 8960/8064 DSI stuff included. But still waiting on the v2 of the
patchset (just pending some minor review comments). It would be nice
to get the DSI patches merged since it would help some folks trying to
get upstream kernel running on n4/n7 and xperia z and wanting to write
some more panel drivers. Also, waiting for OCMEM driver to get merged
via other trees and then I have a small bit to go along with that to
make the gpu actually work on devices w/ OCMEM (snapdragon 800, 805,
etc). So maybe a second later pull req, time permitting.
* 'msm-next' of git://people.freedesktop.org/~robclark/linux:
drm/msm: Remove local fbdev emulation Kconfig option
drm/msm/mdp5: Basic support for MDP5 v1.7 (MSM8996)
drm/msm/mdp: Add Software Pixel Extension support
drm/msm/mdp5: Use the newly introduced enum mdp_component_type
drm/msm/hdmi: Add basic HDMI support for msm8996
drm/msm/mdp5: Avoid printing error messages for optional clocks
drm/msm: Fix IOMMU clean up path in case msm_iommu_new() fails
drm/msm/mdp5: remove the cfg pointer from SMP struct
drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY
drm: msm: dsi: Don't attempt changing voltage of switches
drm/msm: update generated headers
drm/msm: Remove local fbdev emulation Kconfig option
DRM_MSM_FBDEV config is used to enable/disable fbdev emulation for the
msm kms driver.
Replace this with the top level DRM_FBDEV_EMULATION config option where
applicable. This also prevents build breaks caused by undefined
drm_fb_helper_* functions when legacy fbdev support was disabled.
Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
In order to produce an image, the scalar needs to be fed extra
pixels. These top/bottom/left/right values depend on a various of
factors, including resolution, scaling type, phase step and
initial phase.
Pixel Extension are programmed by hardware in most targets - and
can be overwritten by software. For some targets (e.g.: msm8996),
software *must* program those registers.
In order to ease this computation, let's always use bilinear
filters, which are easier to program from kernel. Eventually,
all of these values will come down from user space for better
quality.
Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
drm/msm/mdp5: Use the newly introduced enum mdp_component_type
When calculating phase steps, let's use the same enum
mdp_component_type in order to ease the readability; 0/1 indexes
are a bit confusing and we now have explicit values to index
this type of arrays.
Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
drm/msm/mdp5: Avoid printing error messages for optional clocks
The current behavior is to try to get optional clocks and print a
dev_err message in case of failure. This looks rather confusing
and may increase with the amount of optional clocks.
We may need a cleaner way to handle per-device clocks but in the
meantime, let's reduce the amount of dev_err messages during the
probe.
Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
drm/msm/mdp5: remove the cfg pointer from SMP struct
We want to make sure we control all the information being passed
down to SMP block. Having access to the cfg pointer here may create
bad things in the future.
Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Bjorn Andersson [Tue, 18 Aug 2015 17:34:32 +0000 (10:34 -0700)]
drm: msm: dsi: Don't attempt changing voltage of switches
In some configurations the supplies are voltage switches and not LDOs,
making the set voltage call to fail. Check with the regulator framework
if the supply can change voltage before attempting.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Dave Airlie [Thu, 22 Oct 2015 00:31:43 +0000 (10:31 +1000)]
Merge branch 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev into drm-next
rcar-du support for r8a7793/4
* 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev:
drm: rcar-du: Add support for the R8A7794 DU
drm: rcar-du: Add support for the R8A7793 DU
Dave Airlie [Thu, 22 Oct 2015 00:23:31 +0000 (10:23 +1000)]
Merge tag 'drm-vc4-next-2015-10-21' of http://github.com/anholt/linux into drm-next
This pull request introduces the vc4 driver, for kernel modesetting on
the Raspberry Pi (bcm2835/bcm2836 architectures). It currently
supports a display plane and cursor on the HDMI output. The driver
doesn't do 3D, power management, or overlay planes yet.
[airlied: fixup the enable/disable vblank APIs]
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* tag 'drm-vc4-next-2015-10-21' of http://github.com/anholt/linux:
drm/vc4: Allow vblank to be disabled
drm/vc4: Use the fbdev_cma helpers
drm/vc4: Add KMS support for Raspberry Pi.
drm/vc4: Add devicetree bindings for VC4.
Chunming Zhou [Fri, 16 Oct 2015 06:06:19 +0000 (14:06 +0800)]
drm/amdgpu: fix the broken vm->mutex V2
fix the vm->mutex and ww_mutex confilcts.
vm->mutex is always token first, then ww_mutex.
V2: remove unneccessary checking for pt bo.
Change-Id: Iea56e183752c02831126d06d2f5b7a474a6e4743 Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Eric Anholt [Mon, 2 Mar 2015 21:01:12 +0000 (13:01 -0800)]
drm/vc4: Add KMS support for Raspberry Pi.
This is enough for fbcon and bringing up X using
xf86-video-modesetting. It doesn't support the 3D accelerator or
power management yet.
v2: Drop FB_HELPER select thanks to Archit's patches. Do manual init
ordering instead of using the .load hook. Structure registration
more like tegra's, but still using the typical "component" code.
Drop no-op hooks for atomic_begin and mode_fixup() now that
they're optional. Drop sentinel in Makefile. Fix minor style
nits I noticed on another reread.
v3: Use the new bcm2835 clk driver to manage pixel/HSM clocks instead
of having a fixed video mode. Use exynos-style component driver
matching instead of devicetree nodes to list the component driver
instances. Rename compatibility strings to say bcm2835, and
distinguish pv0/1/2. Clean up some h/vsync code, and add in
interlaced mode setup. Fix up probe/bind error paths. Use
bitops.h macros for vc4_regs.h
v4: Include i2c.h, allow building under COMPILE_TEST, drop msleep now
that other bugs have been fixed, add timeouts to cpu_relax()
loops, rename hpd-gpio to hpd-gpios.
Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Eric Anholt [Tue, 11 Aug 2015 20:17:11 +0000 (13:17 -0700)]
drm/vc4: Add devicetree bindings for VC4.
VC4 is the GPU (display and 3D) subsystem present on the 2835 and some
other Broadcom SoCs.
This binding follows the model of msm, imx, sti, and others, where
there is a subsystem node for the whole GPU, with nodes for the
individual HW components within it.
v2: Extend the commit message, fix several nits from Stephen Warren.
v3: Rename the compatibility strings, clean up node names, drop the
unnecessary lists of components. Use compatibility strings for
choosing CRTC HVS channel numbers. Document the HDMI clock usage.
v4: Whitespace fix, expand acronyms, move to display/ instead of gpu/,
rename "hpd-gpio" to "hpd-gpios".
Lukas Wunner [Sun, 18 Oct 2015 11:05:40 +0000 (13:05 +0200)]
vga_switcheroo: Constify vga_switcheroo_handler
vga_switcheroo_client_ops has always been declared const since its
introduction with 26ec685ff9d9 ("vga_switcheroo: Introduce struct
vga_switcheroo_client_ops").
Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Darren Hart <dvhart@linux.intel.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Christian König <christian.koenig@amd.com>. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Liviu Dudau [Tue, 20 Oct 2015 09:23:15 +0000 (10:23 +0100)]
drm/armada: Convert the probe function to the generic drm_of_component_probe()
The armada DRM driver keeps some old platform data compatibility in the
probe function that makes moving to the generic drm_of_component_probe()
a bit more complicated that it should. Refactor the probe function to do
the platform_data processing after the generic probe (and only if that
fails). This way future cleanup can further remove support for it.
Liviu Dudau [Tue, 20 Oct 2015 09:23:12 +0000 (10:23 +0100)]
drm: Introduce generic probe function for component based masters.
A lot of component based DRM drivers use a variant of the same code
as the probe function. They bind the crtc ports in the first iteration
and then scan through the child nodes and bind the encoders attached
to the remote endpoints. Factor the common code into a separate
function called drm_of_component_probe() in order to increase code
reuse.