Kumar Gala [Tue, 1 Jun 2010 15:29:11 +0000 (10:29 -0500)]
powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Poonam Aggrwal [Thu, 13 Jan 2011 16:10:05 +0000 (21:40 +0530)]
powerpc/85xx: Add Support for Freescale P1014 Processor
The P1014 is similar to the P1010 processor with the following differences:
- 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC)
- no eCAN interface. (P1010 has 2 eCAN interfaces)
- Two SGMII interface (P1010 has 3 SGMII)
- No secure boot
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Poonam Aggrwal [Thu, 13 Jan 2011 16:09:27 +0000 (21:39 +0530)]
powerpc/85xx: Add Support for Freescale P1010 Processor
Key Features include of the P1010:
* e500v2 core frequency operation of 500 to 800 MHz
* Power consumption less than 5.0 W at 800 MHz core speed
* Dual SATA 3 Gbps controllers with integrated PHY
* Dual PCI Express controllers
* Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs)
* TCP/IP acceleration and classification capabilities
* IEEE 1588 support
* Lossless flow control
* RGMII, SGMII
* DDR3 with support for a 32-bit data interface (40 bits including ECC),
up to 800 MHz data rate 32/16-bit DDR3 memory controller
* Dedicated security engine featuring trusted boot
* TDM interface
* Dual controller area networks (FlexCAN) controller
* SD/MMC card controller supporting booting from Flash cards
* USB 2.0 host and device controller with an on-chip, high-speed PHY
* Integrated Flash controller (IFC)
* Power Management Controller (PMC)
* Four-channel, general-purpose DMA controller
* I2C controller
* Serial peripheral interface (SPI) controller with master and slave support
* System timers including a periodic interrupt timer, real-time clock,
software watchdog timer, and four general-purpose timers
* Dual DUARTs
Prabhakar [Tue, 18 Jan 2011 03:33:59 +0000 (09:03 +0530)]
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR
CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET.
It should be as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET.
Haiying Wang [Wed, 1 Dec 2010 15:35:31 +0000 (10:35 -0500)]
8xxx/ddr: add support to only compute the ddr sdram size
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Roy Zang [Fri, 7 Jan 2011 06:06:47 +0000 (00:06 -0600)]
fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.
Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jerry Huang [Fri, 7 Jan 2011 05:42:19 +0000 (23:42 -0600)]
fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)
Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 30 Dec 2010 18:09:53 +0000 (12:09 -0600)]
powerpc/8xxx: Refactor SRIO initialization into common code
Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe
controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
Peter Tyser [Tue, 28 Dec 2010 23:47:25 +0000 (17:47 -0600)]
fsl_pci: Update PCIe boot ouput
This change does the following:
- Adds printing of negotiated link width. This information can be
useful when debugging PCIe issues.
- Makes it optional for boards to implement board_serdes_name().
Previously boards that did not implement it would print unsightly
output such as "PCIE1: Connected to <NULL>..."
- Rewords the PCIe boot output to reduce line length and to make it
clear that the "base address XYZ" value refers to the base address of
the internal processor PCIe registers and not a standard PCI BAR
value.
- Changes "PCIE" output to the standard "PCIe"
Before change:
PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 05
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 06 - 06
After change:
PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
PCIe1: Bus 00 - 05
PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
PCIe2: Bus 06 - 06
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 16:30:44 +0000 (10:30 -0600)]
powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code
Remove duplicated code in SBC8548 board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Kumar Gala [Fri, 17 Dec 2010 16:26:44 +0000 (10:26 -0600)]
powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code
Remove duplicated code in SBC8641 board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: Paul Gortmaker <paul.gortmaker@windriver.com>
Kumar Gala [Fri, 17 Dec 2010 16:42:33 +0000 (10:42 -0600)]
powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8610HPCD board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 16:42:01 +0000 (10:42 -0600)]
powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code
Remove duplicated code in P1_P2_RDB boards and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 16:18:07 +0000 (10:18 -0600)]
powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8569MDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 16:13:19 +0000 (10:13 -0600)]
powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8568MDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 16:21:22 +0000 (10:21 -0600)]
powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8548CDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 16:47:36 +0000 (10:47 -0600)]
powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8641HPCN board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 12:01:24 +0000 (06:01 -0600)]
powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8544DS board and utilize the common
fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3
specially to setup the additional memory map region and we utilize a
single LAW to cover the controller.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 13:01:00 +0000 (07:01 -0600)]
powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code
Remove duplicated code in P2020DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 12:53:52 +0000 (06:53 -0600)]
powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8572DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 15 Dec 2010 20:21:41 +0000 (14:21 -0600)]
powerpc/fsl-pci: Add generic code to setup PCIe controllers
Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled. After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.
We also provide a per controller (rather than all) for some systems that
may have special requirements.
Finally, we refactor the code used by the P1022DS to utilize the new
generic code.
Based on patch by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 17 Dec 2010 11:57:25 +0000 (05:57 -0600)]
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup
Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus. Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.
Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
Becky Bruce [Fri, 17 Dec 2010 23:17:59 +0000 (17:17 -0600)]
MPC8xxx DDR: align informational prints
Add spaces to cause the informational prints to line up with
the ones from init_func_ram() in board.c. Output now looks like
this:
....
DRAM: Detected 4096 MB of memory
This U-Boot only supports < 4G of DDR
You could rebuild it with CONFIG_PHYS_64BIT
DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off)
....
The prints from lbc_sdram_init() have also been modified to line
line up and changed to start with "LBC SDRAM" instead of the
confusing "SDRAM".
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Fri, 17 Dec 2010 23:17:56 +0000 (17:17 -0600)]
mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Fri, 17 Dec 2010 23:17:55 +0000 (17:17 -0600)]
mpc85xx/tlb.c: Allow platforms to specify wimge bits
Some platforms might want to override the default wimge=0 for
DDR. Add CONFIG_SYS_PPC_DDR_WIMGE for those platforms to use.
This will initially only be used by TQM85xx, but could be
useful for other boards or testing going forward. Note that
the name of this define is not 85xx-specific. WIMGE is a
fairly universal concept, so any ppc platforms that require
different WIMGE settings for DDR can use the same #define.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Fri, 17 Dec 2010 23:17:54 +0000 (17:17 -0600)]
tqm85xx: create fixed_sdram() to do sdram setup
Also, change this code to use phys_size_t instead of long int.
Using common naming for this function will enable us to use the common
initdram() for 85xx going forward. Other than the type change,
this is just a code rearrange.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 16 Dec 2010 20:28:06 +0000 (14:28 -0600)]
powerpc/85xx: Cleanup SGMII detection and reporting
Use new is_serdes_configured to determine if TSECs are in SGMII mode and
report that on the various boards that use or can be configured in SGMII
mode in board_eth_init() instead of in the PCI init code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Chenhui Zhao [Tue, 4 Jan 2011 09:23:05 +0000 (17:23 +0800)]
fsl_esdhc: Fix esdhc disabled problem on some platforms
Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if "esdhc" isn't defined
in hwconfig env variable.
Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.
Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 15 Dec 2010 10:04:56 +0000 (04:04 -0600)]
powerpc/85xx: Add is_serdes_configured() support for P1021 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 27 Apr 2010 14:20:20 +0000 (09:20 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8544 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 27 Apr 2010 05:05:41 +0000 (00:05 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8569 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 27 Apr 2010 04:44:10 +0000 (23:44 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8568 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 27 Apr 2010 04:25:33 +0000 (23:25 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8548 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 27 Apr 2010 04:09:23 +0000 (23:09 -0500)]
powerpc/85xx: Add is_serdes_configured() support for MPC8572 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 15 Dec 2010 08:49:03 +0000 (02:49 -0600)]
powerpc/85xx: Add is_serdes_configured() support for P2020 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 15 Dec 2010 10:52:48 +0000 (04:52 -0600)]
powerpc/86xx: Add SERDES support on MPC8641 & MPC8610
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES. This mimics the code we have in place
for the 85xx platforms.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Mon, 13 Dec 2010 21:06:44 +0000 (15:06 -0600)]
socrates: rename sdram_setup fixed_sdram()
This will help us go to a fixed initdram() for all 85xx boards going
forward. sdram_setup() had an argument that it didn't need, since the
value was #defined.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 13 Dec 2010 19:46:43 +0000 (14:46 -0500)]
MPC8xxx: Update maintainer entry for Wind River sbc8xxx boards
I've probably got the best chance of getting access to these
boards in order to test things, and since Joe's e-mail is
bouncing, update the MAINTAINERS entry to reflect this.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit changed the behaviour of getenv_yesno() (both the default
behaviour and the documented behaviour for abbreviated arguments)
which resulted in problems in several areas.
In file included from ubifs.h:2137:0,
from ubifs.c:26:
misc.h: In function 'ubifs_idx_key':
misc.h:263:26: warning: dereferencing type-punned pointer will break strict-aliasing rules
seen with gcc version 4.5.1 (Sourcery G++ Lite 2010.09-50).
No functional change.
CC: Stefan Roese <sr@denx.de> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Yanjun Yang [Sun, 26 Dec 2010 02:40:54 +0000 (10:40 +0800)]
LAN91C*: Change chip names to fit the eth_device struct size
The eth_device.name field length is limited by NAMESIZE,
which is 16 defined in include/net.h. Unfortunately, two
of the names in lan91c96.c are beyond that.
Michal Simek [Tue, 21 Dec 2010 08:32:44 +0000 (09:32 +0100)]
microblaze: Fix bd_info pointer
Patch "Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value"
(sha1: 25ddd1fb0a2281b182529afbc8fda5de2dc16d96)
introduce GENERATED_GBL_DATA_SIZE which is sizeof aligned gd_t
(currently 0x40).
Microblaze configs used 0x40(128) because this place also contained
board info structure which lies on the top of ram.
U-Boot is placed to the top of the ram (for example 0xd7ffffff)
and bd structure was moved out of ram.
This patch is fixing this scheme with GENERATED_BD_INFO_SIZE
which swap global data and board info structures.
Michal Simek [Tue, 21 Dec 2010 07:30:39 +0000 (08:30 +0100)]
microblaze: Disabling interrupt should return 1 if was enabled
Microblaze implement enable/disable interrupts through MSR
that's why disable_interrupts function should return 1 when interrupt
was enabled. Return 0 when interrupt was disabled.
Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Wolfgang Denk <wd@denx.de>
Chris Packham [Sun, 19 Dec 2010 10:12:13 +0000 (10:12 +0000)]
pca953x: support 16-pin devices
This adds support for for the PCA9535/PCA9539 family of gpio devices which
have 16 output pins.
To let the driver know which devices are 16-pin it is necessary to define
CONFIG_SYS_I2C_PCA953X_WIDTH in your board config file. This is used to
create an array of {chip, ngpio} tuples that are used to determine the
width of a particular chip. For backwards compatibility it is assumed that
any chip not defined in CONFIG_SYS_I2C_PCA953X_WIDTH has 8 pins.
Acked-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Mike Frysinger [Fri, 24 Dec 2010 17:57:23 +0000 (12:57 -0500)]
asm-offsets: generate bd_t size
Some ports set up the board info structure at the same time as the global
data structure, and largely keep them together. So generate a define for
the board info struct too.
Mike Frysinger [Thu, 23 Dec 2010 20:40:12 +0000 (15:40 -0500)]
miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Mike Frysinger [Tue, 21 Dec 2010 19:08:27 +0000 (14:08 -0500)]
load_addr: move to common env code
Rather than keep the load_addr definition with the bootm code (which
just happens to use this), move it to the common env code. This way
we can disable bootm support completely while retaining load_addr
usage with many other commands.
projects / karo-tx-uboot.git / log