Daniel Vetter [Thu, 29 May 2014 21:23:08 +0000 (23:23 +0200)]
drm/i915: Fix context locking in debugfs
This goes all the way back to the introduction of this debugfs file,
even though back then no locking really was required. None of the
intermediate patches fixed this.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau [Wed, 28 May 2014 11:30:56 +0000 (12:30 +0100)]
drm/i915: Make intel_dsi_init() return void
Functions that can't fail are such a bliss to work with, it'd be shame
to miss the occasion. The "failure" mode is the DSI connector not being
created, the rest of the initialization can carry on happily.
We weren't even checking that value anyway.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Shobhit Kumar <shobhit.kumar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Also convert the missed return statement due to other patches
merged meanwhile.]
[danvet2: Squash in fixup from Damien to remove empty return; at the
end of intel_dsi_init.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 9 Apr 2014 10:29:09 +0000 (13:29 +0300)]
drm/i915/chv: Handle video DIP registers on CHV
The DIP registers are a mess on VLV and CHV. The register block on pipe
A is different than the register block on pipes B and C. In order to
handle that using the pipe offsets, we'd need a new pipe offset per
register, which seems wasteful. So instead just use the _PIPE3() macro
to handle these registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 27 May 2014 13:32:55 +0000 (16:32 +0300)]
drm/i915/chv: Force PHY clock buffers off after PLL disable
Now that we forced the clock buffers on in .pre_pll_enable() we
should probably undo the damage after we've turned the PLL off.
We do the clock buffer force enable in the .pre_pll_enable() hook
as we need to know which port is going to be used, but in the disable
case we don't need the port since we just disable the clock buffers
to both channels. So we can do this in chv_disable_pll() instead
of having to add any kind of .post_pll_disable() hook.
v2: Improve the commit message
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 27 May 2014 13:30:18 +0000 (16:30 +0300)]
drm/i915/chv: Force clock buffer enables
Try to force the PHY clock buffer enables to make the clock routing
work.
v2: Fix the pipe B case to actually enable CH0 clock buffers
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Wed, 9 Apr 2014 10:29:05 +0000 (13:29 +0300)]
drm/i915/chv: Try to program the PHY used clock channel overrides
These should make it possible to feed port C from pipe A or port B from
pipe B. Didn't quite seem to work though.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 23 May 2014 15:30:19 +0000 (21:00 +0530)]
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.
This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Fri, 23 May 2014 15:30:18 +0000 (21:00 +0530)]
drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
Skip __gen6_gt_wait_for_thread_c0() on CHV.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Deepak S [Tue, 27 May 2014 10:29:30 +0000 (15:59 +0530)]
drm/i915/chv: Enable RPS (Turbo) for Cherryview
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv->rps variables in upstream.
v4: Rebase against latest code. (Deepak)
v5: Rebase against latest nightly code. (Deepak)
v6: Rename the variables to match the spec (Mika)
v7: change min/max freq variable naming to match spec (Mika)
Signed-off-by: Deepak S <deepak.s@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 22 May 2014 14:48:06 +0000 (17:48 +0300)]
drm/i915: Keep vblank interrupts enabled while enabling/disabling planes
Because of the upcoming vblank interrupt driven watermark update
mechanism we will have use for vblank interrupts during plane
enabling/disabling. So don't call drm_vblank_off() until planes
are off, and call drm_vblank_on() just before we start to enable
the planes.
v2: Pimp commit message (Paulo)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Deepak S [Fri, 23 May 2014 15:30:16 +0000 (21:00 +0530)]
drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.
v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
Re-factor CHV/VLV Forcewake offsets (Ben)
v3: Fix for decrementing fw count in chv read/write. (Deepak)
v4: Squash the patches (Mika)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[vsyrjala: Move the register range macros into intel_uncore.c] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Deepak S [Fri, 23 May 2014 15:30:15 +0000 (21:00 +0530)]
drm/i915/chv: Enable Render Standby (RC6) for Cherryview
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
v3: Fix PCBR condition check during CHV RC6 Enable flag set
v4: Fixup PCBR comment msg. (Chris)
Rebase against latest code (Deak)
Fixup Spurious hunk (Ben)
v5: Fix PCBR and commentis msg (mika)
v6: Rebase patch on latest nightly (Deepak)
Signed-off-by: Deepak S <deepak.s@linux.intel.com> Acked-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rodrigo Vivi [Fri, 23 May 2014 20:45:51 +0000 (13:45 -0700)]
drm/i915: move psr_setup_done to psr struct
"Because our driver assumes only one panel is PSR capable, and we
already have other PSR information on dev_priv instead of intel_dp. If
we ever support multiple PSR panels, we'll have to move struct
i915_psr to intel_dp anyway." (by Paulo)
v2: Avoid more than one setup. Removing initialization
and trusting allocation. (By Paulo Zanoni).
v3: rebase.
v4: Adding comment.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Dave Airlie [Wed, 11 Jun 2014 06:28:10 +0000 (16:28 +1000)]
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
display rework fixes lots of displayport issues.
* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (43 commits)
drm/nouveau/disp/dp: fix tmds passthrough on dp connector
drm/nouveau/dp: probe dpcd to determine connectedness
drm/nv50-: trigger update after all connectors disabled
drm/nv50-: prepare for attaching a SOR to multiple heads
drm/gf119-/disp: fix debug output on update failure
drm/nouveau/disp/dp: make use of postcursor when its available
drm/g94-/disp/dp: take max pullup value across all lanes
drm/nouveau/bios/dp: parse lane postcursor data
drm/nouveau/dp: fix support for dpms
drm/nouveau: register a drm_dp_aux channel for each dp connector
drm/g94-/disp: add method to power-off dp lanes
drm/nouveau/disp/dp: maintain link in response to hpd signal
drm/g94-/disp: bash and wait for something after changing lane power regs
drm/nouveau/disp/dp: split link config/power into two steps
drm/nv50/disp: train PIOR-attached DP from second supervisor
drm/nouveau/disp/dp: make use of existing output data for link training
drm/gf119/disp: start removing direct vbios parsing from supervisor
drm/nv50/disp: start removing direct vbios parsing from supervisor
drm/nouveau/disp/dp: maintain receiver caps in response to hpd signal
drm/nouveau/disp/dp: create subclass for dp outputs
...
Ben Skeggs [Fri, 30 May 2014 15:48:06 +0000 (01:48 +1000)]
drm/nouveau/dp: fix support for dpms
SOR_PWR has no effect to power-off DP links, unlike other SOR protocols.
Instead, on the source side, we cut power to the lanes after having put
the sink into D3. Link training takes care of everything required to
bring it back again.
Ben Skeggs [Tue, 20 May 2014 00:18:03 +0000 (10:18 +1000)]
drm/nouveau/disp/dp: maintain link in response to hpd signal
This previously worked for the most part due to userspace doing a
modeset in response to HPD interrupts. This will allow us to
properly handle cases where sync is lost for other reasons, or if
userspace isn't caring.
Ben Skeggs [Fri, 16 May 2014 04:36:15 +0000 (14:36 +1000)]
drm/nouveau/disp: add internal representaion of output paths and connectors
This will, at some point, be used to replace various bits and pieces of
code doing direct bios parsing. For now, it'll just be used for some
DP improvements.
Ben Skeggs [Thu, 29 May 2014 01:07:16 +0000 (11:07 +1000)]
drm/nouveau/i2c: balance port acquire/release
This was a half-finished hack before, just enough to handle the shared
aux/i2c pad thing on G94 and up.
We got lucky with locking etc up until now, as this was (generally) all
protected by the DRM mode_config lock. It's about to become a lot more
likely to hit the races.
Dave Airlie [Tue, 10 Jun 2014 06:39:21 +0000 (16:39 +1000)]
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
There's really not a great deal this time due to me spending most of this window on Maxwell. But, here's the random bits and pieces that's currently queued.
* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (25 commits)
drm/gk208/gr: add missing registers to grctx init
drm/nouveau/kms/nv04-nv40: fix pageflip events via special case.
drm/nv50-/mc: fix kms pageflip events by reordering irq handling order.
drm/nouveau/disp/nv04-nv40: abort scanoutpos query on vga analog.
drm/nv50-/kms: wait for enough ring space in crtc_prepare()
drm/nouveau/disp/dp: support training pattern 3
drm/nouveau/disp/dp: support aux read interval during link training
drm/gk104/gpio: fix incorrect interrupt register usage
drm/nouveau/core: punt all object state change messages to trace level
drm/nouveau/clk: allow end-user reclocking for nv40, nvaa, and nve0 clock types
drm/nouveau/fb: default NvMemExec to on, turning it off is used for debugging only
drm/nouveau/bios: fix a potential NULL deref in the PROM shadowing function
drm/nouveau/i2c: bump the i2c delay for the adt7473
drm/nouveau/therm/fan/tach: default to 2 pulses per revolution
drm/nvf0/device: enable video decoding engines on gk110/gk208
drm/nvf1/device: add support for 0xf1 (gk110b)
drm/nouveau/device: support for probing GK20A
drm/nouveau/graph: add GK20A support
drm/nouveau/graph: pad firmware code at load time
drm/nouveau/graph: enable when using external fw
...
Mario Kleiner [Mon, 12 May 2014 22:42:08 +0000 (00:42 +0200)]
drm/nouveau/kms/nv04-nv40: fix pageflip events via special case.
Cards with nv04 display engine can't reliably use vblank
counts and timestamps computed via drm_handle_vblank(), as
the function gets invoked after sending the pageflip events.
Fix this by defaulting to the old crtcid = -1 fallback path
on <= NV-50 cards, and only using the precise path on NV-50
and later.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: <stable@vger.kernel.org> # 3.13+
Mario Kleiner [Wed, 19 Mar 2014 07:12:51 +0000 (08:12 +0100)]
drm/nv50-/mc: fix kms pageflip events by reordering irq handling order.
Whenever a single nouveau_mc_intr() main gpu irq-handler invocation was
responsible for calling both, the vblank-irq handler (display engine irq)
and kms-pageflip completion handler (from fifo irq), the order of
invocation was wrong. nouveau_finish_flip() was called before
drm_handle_vblank() for the vblank of pageflip completion, so the
emitted pageflip event contained stale vblank count and timestamp
from previous vblank. This caused failure in userspace to timestamp
properly.
Reorder order of invocation of engine irq handlers: Put
NVDEV_ENGINE_DISP always on top, and thereby before NVDEV_ENGINE_FIFO,
so that drm_handle_vblank() gets called to update vblank timestamps
and count before potential pageflip events make use of that
information.
This works on nv-50 and later, where kms-pageflip completion triggers
an irq either after a separate vblank irq, or both pageflip and vblank
trigger one common irq invocation, but never before vblank irqs.
v2 (Ben):
- removed mods for nv04-nv40, it doesn't help there anyway
- this is considered a hack, and a better solution should be found
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: <stable@vger.kernel.org> # 3.13+
Mario Kleiner [Wed, 28 May 2014 03:22:18 +0000 (05:22 +0200)]
drm/nouveau/disp/nv04-nv40: abort scanoutpos query on vga analog.
nv04_disp_scanoutpos() must abort to trigger simple timestamping
fallback if vtotal/htotal regs return zero. This happens if the
output isn't a digital output, but a vga analog output, as the
regs don't get initialized in that case.
Fixes timestamping failure on nv-40 and earlier with vga output.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: <stable@vger.kernel.org> # 3.14+
Martin Peres [Thu, 3 Apr 2014 20:12:41 +0000 (22:12 +0200)]
drm/nouveau/bios: fix a potential NULL deref in the PROM shadowing function
Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Martin Peres [Mon, 12 May 2014 21:19:07 +0000 (23:19 +0200)]
drm/nouveau/therm/fan/tach: default to 2 pulses per revolution
I spent some time this weekend trying to find in the vbios the number of
pulses per revolutions in the vbios but couldn't find it. It would seem
all my cards have 2 pulses per revolution so let's stick to that until
further notice.
Thermal table's id 0x48 may indicate this information but it would seem
that changing the value results in the blob power or clock gating the
RPM counter... We should ask NVIDIA about that, should be trivial-enough
for them to answer.
Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
nvc0_graph_ctor() would only let the graphics engine be enabled if its
oclass has a proper microcode linked to it. This prevents GR from being
enabled at all on chips that rely exclusively on external firmware, even
though such a use-case is valid.
Relax the conditions enabling the GR engine to also include the case
where an external firmware has also been loaded.
Also switch to external firmware if the graph class has no microcode
linked to it.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Dave Airlie [Tue, 10 Jun 2014 03:09:01 +0000 (13:09 +1000)]
Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm-next
Some additional patches for radeon for 3.16 now that -fixes has been merged.
- Gart fix for all asics r6xx+
- Add some VM tuning parameters
- misc fixes
* 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: Move fb update from radeon_flip_work_func to radeon_crtc_page_flip
drm/radeon/dpm: powertune updates for SI
Revert "drm/radeon: use variable UVD clocks"
drm/radeon: add query for number of active CUs
drm/radeon: add debugfs file to trigger GPU reset
drm/radeon: make vm_block_size a module parameter
drm/radeon: make VM size a module parameter (v2)
drm/radeon: rename alt_domain to allowed_domains
drm/radeon: use the SDMA on for buffer moves on CIK again
drm/radeon: remove range check from *_gart_set_page
drm/radeon: stop poisoning the GART TLB
drm/radeon: hdmi deep color modes must obey clock limit of sink.
drm/edid: Store all supported hdmi deep color modes in drm_display_info
drm/radeon: add missing vce init case for hawaii
drm/radeon: use lower_32_bits where appropriate
Michel Dänzer [Tue, 10 Jun 2014 01:21:57 +0000 (10:21 +0900)]
drm/radeon: Move fb update from radeon_flip_work_func to radeon_crtc_page_flip
Fixes WARN()s from the DRM core since the page flip rework.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=77521 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Sat, 7 Jun 2014 15:31:25 +0000 (11:31 -0400)]
Revert "drm/radeon: use variable UVD clocks"
This caused reduced performance for some users with advanced post
processing enabled. We need a better method to pick the
UVD state based on the amount of post processing required or tune
the advanced post processing to fit within the lower power state
envelope.
Christian König [Mon, 2 Jun 2014 15:33:07 +0000 (17:33 +0200)]
drm/radeon: rename alt_domain to allowed_domains
And also domain to prefered_domains. That matches better
what those values represent.
Signed-off-by: Christian König <christian.koenig@amd.com> Cc: Marek Olšák <maraeo@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 4 Jun 2014 13:29:56 +0000 (15:29 +0200)]
drm/radeon: stop poisoning the GART TLB
When we set the valid bit on invalid GART entries they are
loaded into the TLB when an adjacent entry is loaded. This
poisons the TLB with invalid entries which are sometimes
not correctly removed on TLB flush.
For stable inclusion the patch probably needs to be modified a bit.
Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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