Shengjiu Wang [Thu, 4 Sep 2014 02:52:45 +0000 (10:52 +0800)]
ENGR00329948-2: dma: imx-sdma: Add device to device support
This patch adds DEV_TO_DEV support for i.MX SDMA driver to support data
tranfer between two peripheral FIFOs. The per_2_per script requires two
peripheral addresses and two DMA requests, a bit different from the other
scripts.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
ENGR00330358 ARM: IMX6SL-EVK: PXP-V4L2: add pxp v4l2 support to 3.14 branch
1. Add the 'pxp_v4l2_out' entry to imx6sl-evk.dtb to enable
the pxp v4l2 output driver.
2. Correct the backlight device node position in imx6sl-evk.dtb.
ENGR00330163 ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL
clocks are not the same. So split the epdc_pxp_sels into two different
clock selections 'pxp_axi_sels' and 'epdc_axi_sels'.
Dong Aisheng [Wed, 27 Aug 2014 07:55:59 +0000 (15:55 +0800)]
ENGR00329352-1 regmap: regmap-mmio: make clk_id optionally when getting clock
According to clock framework, the clk_id could be NULL when getting clock.
But current code relies on a non null clk_id to get clock.
Changing the code to allow a null clk_id to get clock to make it more
reasonable to use.
And the regmap_mmio_gen_context will try to get clock by default but ignore
error if not finding the clock in case some regmap access not reply on
a specific clock.
Dong Aisheng [Thu, 26 Jun 2014 09:39:15 +0000 (17:39 +0800)]
ENGR00320355 dts: imx6: mmc index fixed by controller order
Make the linux mmc index to be fixed according to controller order.
This can make user easily to identify which mmcX corresponding to which
controller and kernel be able find the rootfs in a card plugged in a
specific slot persistently.
This is a eventually solution for finding mmc block devices correctly
for different cards on multi slots.
Sascha Hauer [Fri, 20 Jun 2014 07:08:16 +0000 (15:08 +0800)]
mmc: Allow setting slot index via devicetree alias
As with gpio, uart and others, allow specifying the name_idx via the
aliases-node in the devicetree.
On embedded devices, there is often a combination of removable (e.g.
SD card) and non-removable mmc devices (e.g. eMMC).
Therefore the name_idx might change depending on
- host of removable device
- removable card present or not
This makes it difficult to hard code the root device, if it is on the
non-removable device. E.g. if SD card is present eMMC will be mmcblk1,
if SD card is not present at boot, eMMC will be mmcblk0.
If the aliases-node is not found, the driver will act as before.
The original patch is from here:
https://www.mail-archive.com/linux-mmc@vger.kernel.org/msg26472.html
The patch requires additional alias_id fix or it won't work.
Because according to function definition the max_idx parameter of idx_alloc
is exclusive, so need add 1 or it will be unable to find the proper idx
within an invalid range.
Sascha Hauer [Thu, 22 May 2014 15:30:22 +0000 (17:30 +0200)]
of: Add helper for getting the maximum alias index for a stem
of_alias_max_index will return the maximum number for which an
alias of a given stem exists. This is useful for frameworks
whishing to reserve a number of device slots from dynamic
allocation.
ENGR00323682 MMC: Fixed boot_config overwritten by switch partition
In MMC driver, two variables: boot_config and part_config are used to
keep eCSD(179) PARTITION_CONFIG. The part_config is not updated when
set new boot_config, which causes the eCSD(179) is overwritten by
any following partition switching, so the new boot_config is lost.
ENGR00329475-5 ARM: imx: make sure OCOTP clk is enabled in MSL
As some modules need to access ocotp in MSL, so we need to
make sure it is enabled during MSL, after kernel boot up,
clk dirver will disable it in late init.
ENGR00329475-4 ARM: imx: support perclk and uart clk parent to OSC on i.mx6sx
change perclk parent to OSC instead of IPG, as IPG clock may
be changed by busfreq.
when kernel command line has "uart_from_osc" defined, uart clk will
select OSC as its parent, this is to make PLL3 be able to be off
for low power purpose, as we need all PLLs off in low power idle
mode.
ENGR00329475-2 ARM: imx: correct gpu2d_axi and gpu3d_axi clock setting
On i.MX6Q, gpu2d_axi and gpu3d_axi are either from AXI or
AHB clock, but on i.MX6DL, gpu2d_axi and gpu3d_axi are
from mmdc_ch0_axi_podf, and they can NOT be gated by mmdc_ch0_axi
's clock gate, the mux option register field(CCM_CBCMR)
is marked as "Reserved" now on i.MX6DL RM, so correct these
two clks setting.
clk: Support for clock parents and rates assigned from device tree
This patch adds helper functions to configure clock parents and rates
as specified through 'assigned-clock-parents', 'assigned-clock-rates'
DT properties for a clock provider or clock consumer device.
The helpers are now being called by the bus code for the platform, I2C
and SPI busses, before the driver probing and also in the clock core
after registration of a clock provider.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
[shawn.guo: cherry-pick commit 86be408bfbd8 from upstream] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds of_clk_get_by_clkspec() helper function, which does only
a struct clk lookup from the clock providers. It is used in the subsequent
patch where parsing of a clock from device tree and the lookup from
providers needed to be split.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
[shawn.guo: cherry-pick commit 7f05e28f9dd3 from upstream] Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
luweizhou [Tue, 24 Jun 2014 04:15:00 +0000 (12:15 +0800)]
ENGR00314144 mxc: mlb: Rename the mxc_mlb150 to mxc_mlb.
Since i.MX6SX doesn't supports MLB150 , it is not strictly explicit to
name driver module as mxc_mlb150.ko. Rename it to mxc_mlb.ko.It would be
more common.
ENGR00311027 gpu:Limit the memory consumption for webgl
-When system memory is less than 200M, we will block further
memory allocation for webgl.
It's for pass webgl 1.0.2 conformance case conformance/rendering/multisample-cor
ruption.html
It's a temperory patch from vivante, should be removed in 5.0.11p2.
Original patch name:5x_crash_patch.diff
Conflict:
drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c
Revert "ENGR00317981: gpu-viv: use runtime pm for VDDPU management" and
move the same change logic to file gc_hal_kernel_platform_imx6q14.c for
following p1 framework change.
With commit 4ed95424c715 ("ARM: 8122/1: smp_scu: enable SCU standby
support"), the STANDBY bit of SCU is handled by core function
scu_enable(). So imx_scu_standby_enable() can be removed now.
With SCU standby enabled, SCU CLK will be turned off when all processors
are in WFI mode. And the clock will be turned on when any processor
leaves WFI mode.
This behavior should be preferable in terms of power efficiency of
system idle. So let's set the SCU standby bit to enable the support in
function scu_enable().
Cortex-A9 earlier than r2p0 has no standby bit in SCU, so we need to
skip setting the bit for those.
shawn.guo: cherry-pick commit c716483c3db1 from upstream
Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 8103/1: save/restore Cortex-A9 CP15 registers on suspend/resume
The CP15 diagnostic register holds ARM errata bits on Cortex-A9, so it
needs to be saved/restored on suspend/resume. Otherwise, the
effectiveness of errata workaround gets lost together with diagnostic
register bit across suspend/resume cycle. And the CP15 power control
register of Cortex-A9 shares the same problem.
The patch adds a couple of Cortex-A9 specific suspend/resume functions
to save/restore these two Cortex-A9 CP15 registers across the
suspend/resume cycle.
shawn.guo: cherry-pick commit ddd0c5301822 from upstream
Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
i2c: imx: fix the i2c bus hang issue when do repeat restart
Test i2c device Maxim max44009, datasheet is located at:
http://www.maximintegrated.com/datasheet/index.mvp/id/7175
The max44009 support repeat operation like:
read -> repeat restart -> read/write
The current i2c imx host controller driver don't support this
operation that causes i2c bus hang due to "MTX" is cleared in
.i2c_imx_read(). If "read" is the last message there have no problem,
so the current driver supports all SMbus operation like:
write -> repeat restart -> read/write
IMX i2c controller for master receiver has some limitation:
- If it is the last byte for one operation, it must generate STOP
signal before read I2DR to prevent controller from generating another
clock cycle.
- If it is the last byte in the read, and then do repeat restart, it must
set "MTX" before read I2DR to prevent controller from generating another
extra clock cycle.
The patch is to fix the issue.
Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 054b62d9f25c903958749e4cea25261324a7a2a4)
Nicolin Chen [Mon, 16 Jun 2014 03:32:29 +0000 (11:32 +0800)]
dmaengine: imx-sdma: Save imx_dma_data into sdmac
The filter() function is currently called by xlate() while it transfers
imx_dma_data as a local variable to the filter() but releases the data
right after returning a DMA channel pointer, which results chan->private
pointing an invalid memory space.
So this patch just stores the imx_dma_data into sdmac to make usre the
private pointer valid as long as the channel exists.
fsl_asoc_xlate_tdm_slot_mask() is different with snd_soc_xlate_tdm_slot_mask().
fsl_asoc_xlate_tdm_slot_mask() will set the enabled bit to 0, disabled bit
to 1. snd_soc_xlate_tdm_slot_mask() will set the enabled bit to 1, disabled
bit to 0.
For esai when the bit value is 1, the slot is enabled, when the bit value is 0,
the slot is disabled. If using fsl_asoc_xlate_tdm_slot_mask(), the esai will
work abnormally. So revert this patch, make the esai use default function.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 769091ee18056b3aa35b415d9768fb23f361e598)
Mark Brown [Fri, 1 Aug 2014 16:55:55 +0000 (17:55 +0100)]
ASoC: imx-audmux: Use uintptr_t for port numbers
Since we pass the port number through file private data for debugfs we cast
it to and from a pointer so use uintptr_t in order to ensure that the
types are compatible, avoiding warnings on 64 bit platforms where pointers
are 64 bit and unsigned integers 32 bit.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 4e13eb722153a5ad66edd80bc26c3028d96a7b93)
303
304 if (pair && asrc_priv->pair[pair->index] == pair)
^^^^
Check.
305 asrc_priv->pair[pair->index] = NULL;
306
So we just let the driver check pair before using it.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 6ccf62c7bea561cca7ffbd50839f883327080800)
DPCM needs extra dapm routes in the machine driver to route audio
between Front-End and Back-End. In order to differ the stream names
in the route map from CODECs, we here add specific stream names to
SSI driver so that we can implement ASRC via DPCM to it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Timur Tabi <timur@tabi.org> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit e365500459095276d19a920d5be1a65d0ef9999c)
DPCM needs extra dapm routes in the machine driver to route audio
between Front-End and Back-End. In order to differ the stream names
in the route map from CODECs, we here add specific stream names to
SPDIF driver so that we can implement ASRC via DPCM to it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 756409320bcb366aa5954b4162612aa4be7e37a4)
DPCM needs extra dapm routes in the machine driver to route audio
between Front-End and Back-End. In order to differ the stream names
in the route map from CODECs, we here add specific stream names to
SAI driver so that we can implement ASRC via DPCM to it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 20d5b76fb2c7070c70fc91b666f5395e5d16e197)
DPCM needs extra dapm routes in the machine driver to route audio
between Front-End and Back-End. In order to differ the stream names
in the route map from CODECs, we here add specific stream names to
ESAI driver so that we can implement ASRC via DPCM to it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 74ccb27c35c799a14933c282c4e3c864886fc429)
Dan Carpenter [Thu, 31 Jul 2014 09:32:09 +0000 (12:32 +0300)]
ASoC: fsl_asrc: fix an error code in fsl_asrc_probe()
There is a cut and paste bug so it returns success instead of the error
code.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit d387dd08e444b22f844475780fe12a1ad1c6fffd)
Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit d526416c4fb23a48ed2547138c43e96fa3901124)
Let SND_SOC_FSL_ASRC select SND_SOC_GENERIC_DMAENGINE_PCM in order to fix such
error.
Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit bdb9eb49671566afb9ca2025752f57d0e1a6b2a3)
Fix the following build errors that were observed by building with
make ARCH=microblaze allyesconfig:
>> sound/soc/fsl/fsl_asrc.c:906:5: warning: "CONFIG_PM_RUNTIME" is not defined [-Wundef]
#if CONFIG_PM_RUNTIME
^
>> sound/soc/fsl/fsl_asrc.c:934:5: warning: "CONFIG_PM_SLEEP" is not defined [-Wundef]
#if CONFIG_PM_SLEEP
^
>> sound/soc/fsl/fsl_asrc.c:906:5: warning: "CONFIG_PM_RUNTIME" is not defined [-Wundef]
#if CONFIG_PM_RUNTIME
^
>> sound/soc/fsl/fsl_asrc.c:934:5: warning: "CONFIG_PM_SLEEP" is not defined [-Wundef]
#if CONFIG_PM_SLEEP
Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit d3dacda9390b936a1c341d868f548944cc1c70de)
ASoC: fsl_asrc: Add ASRC ASoC CPU DAI and platform drivers
The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a different
output clock. The driver currently works as a Front End of DPCM with other Back
Ends DAI links such as ESAI<->CS42888 and SSI<->WM8962 and SAI. It converts the
original sample rate to a common rate supported by Back Ends for playback while
converts the common rate of Back Ends to a desired rate for capture. It has 3
pairs to support three different substreams within totally 10 channels.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: Varka Bhadram <varkabhadram@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 3117bb3109dc223e186302f5dc8ce9ed04adca90)
ASoC: fsl_sai: Improve enable flow in fsl_sai_trigger()
The previous enable flow:
1, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO)
2, Mask IRQ of Tx/Rx to enable its interrupt.
3, Enable DMA request of Tx/Rx.
As this flow would enable DMA request later than TERE, the Tx FIFO
would be easily emptied into underrun while Rx FIFO would be easily
stuffed into overrun due to the delayed DMA transfering.
This issue happened merely occational before the patch 'ASoC: fsl_sai:
Reset FIFOs after disabling TE/RE' because there were useless data
remaining in the FIFO for the gap. However, it manifested after FIFO
reset's implemented.
After this patch, the new flow:
1, Enable DMA request of Tx/Rx.
2, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO)
3, Mask IRQ of Tx/Rx to enable its interrupt.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit a3fdc6749edf4dcb07df3a10bbdd9850ed5fd01a)
ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unset
TE/RE bit of T/RCSR will remain set untill the current frame is physically
finished. The FIFO reset operation should wait this bit's totally cleared
rather than ignoring its status which might cause TE/RE disabling failed.
This patch adds delay and timeout to wait for its completion before FIFO
reset.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit c44b56af9ca3a6f135d8f22b9a240f53909b371e)
ASoC: fsl_sai: Reduce race condition during TE/RE enabling
For trigger start, we don't need to check if it's the first time to
enable TE/RE or second time. It doesn't hurt to enable them any way,
which in the meantime can reduce race condition for TE/RE enabling.
For trigger stop, we will definitely clear FRDE of current direction.
Thus the driver only needs to read the opposite one's.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit f4075a8f452aff5465c6522c92da9db71ed11b7f)
ASoC: fsl_sai: Fix incorrect register writing in fsl_sai_isr()
In the rx irq handling part, we should clear the flags in RCSR not TCSR.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 4800f88b615f194ae3c1577038a7ccd871c907c9)
SAI will not clear their FIFOs after disabling TE/RE. Therfore, the driver
should take care the task so as not to let useless data remain in the FIFO.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit eff952b733d4c1ff3a6b35accce940b223372978)
I received a report this morning from one of the Novena developers that
the behaviour of the iMX6 ASoC codec driver (using imx-pcm-dma.c) was
sub-optimal under high system load.
While there are issues relating to system load remaining, upon reviewing
the ASoC imx-pcm-dma.c driver, it was noticed that it not using the
residue support, because SDMA doesn't support it. This has the effect
that SDMA has to make multiple calls into the ASoC and ALSA code, one
for each period.
Since ALSA's snd_pcm_elapsed() does not need to be called multiple times
and it is entirely sufficient to call it once to update ALSA with the
current buffer position via the pointer method, we can do better here.
We can also avoid stopping the DMA entirely, just like real cyclic DMA
implementations behave. While this means that we replay some old samples,
this is a nicer behaviour than having audio stop and restart.
The changes to achieve this are relatively minor - imx-sdma.c can track
where the DMA is to the nearest descriptor boundary - it does this
already when deciding how many callbacks to issue. In doing this,
buf_tail always points at the descriptor which will complete next.
The residue is defined by the bytes remaining to the end of the buffer,
when the buffer is viewed as a single block of memory [start...end].
So, when we start out, there's a full buffer worth of residue, and this
counts down as we approach the end of the buffer, eventually becoming
zero at the end, before returning to the full buffer worth when we
wrap back to the start.
Moving the walking of the descriptors into the interrupt handler means
that we can update the BD_DONE flag at interrupt time, thus avoiding
a delayed tasklet stopping the cyclic DMA.
This means that the residue can be calculated from (total descriptors -
buf_tail) * descriptor size. This is what the change below does. We
update imx-pcm-dma.c to remove the NO_RESIDUE flag since we now provide
the residue.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
(cherry picked from commit d1a792f3b4072bfac4150bb62aa34917b77fdb6d)
Arnd Bergmann [Tue, 3 Jun 2014 12:11:56 +0000 (14:11 +0200)]
ASoC: fsl: refine DMA/FIQ dependencies
Commit 31ee2bfd724ab ("ASoC: fsl: select SND_SOC_IMX_PCM_DMA
where needed") started selecting SND_SOC_IMX_PCM_DMA and
SND_SOC_IMX_PCM_FIQ for two drivers when building for i.MX.
This has turned out too aggressive, as FIQ is only available
for i.mx2 through i.mx5, but not i.mx6 or vybrid.
Further, two more drivers have become user-selectable in the
meantime, and they both depend on DMA for the imx platform
as well.
This changes the selection of FIQ to depend on the TZIC or
AVIC interrupt controllers that actually export the imx
specific FIQ interfaces, and adds the missing select statements
for SAI and ESAI.
Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit ff40260f79dc0436604452bccd449bffd25ebafb)
Simplify error handling and remove repetitive (and rarely executed) code
for unregistration by providing a devm_snd_soc_register_platform()
platform.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 8931bf6208776292b1b888dd8534229f63e2eaa2)
ARM: imx: Add the secondary request into the structure for imx-sdma
SDMA supports device to device (per_2_per) scripts to handle DMA transfering
between two peripheral devices. The per_2_per script, however, needs two dma
requests from two sides while the current structure only defined one request.
So this patch just simply adds the secondary request so as to let SDMA and
its user to add its implementation later.
[ Both change in the SDMA driver and its users like Freescale ASRC ASoC driver
should be taken along with this change in order to truly support per_2_per
sciprts. However, we here make an expediency by adding this first so that
we can add either side later since this patch won't break any function and
meanwhile it can make merge window more smoothly: we don't need to apply the
change inside dmaengine branch via ASoC tree any more. -- Nicolin ]
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 94b912e42829b25d97b6b1f2be66c6aa81ac125f)
Anson Huang [Fri, 20 Jun 2014 06:01:46 +0000 (14:01 +0800)]
ENGR00319456-2 cpufreq: imx6: correct regulator API
for PU regulator, if we do NOT want a dummy regulator
returned when there is no PU regulator available,
devm_regulator_get_optional should be used instead
of devm_regulator_get.
Anson Huang [Fri, 20 Jun 2014 05:59:55 +0000 (13:59 +0800)]
ENGR00319456-1 regulator: core: remove incorrect change of regulator_get
If user do NOT want a dummy regulator returned when
there is no matching regulator found, then they should use
regulator_get_optional instead of regulator_get. So remove
incorrect change.
Anson Huang [Thu, 19 Jun 2014 01:01:58 +0000 (09:01 +0800)]
ENGR00318913-5 cpufreq: imx6: remove pu regulator dependency
PU regulator is not a necessary regulator for cpufreq, not all
i.MX6 SoCs have PU regulator, so remove the dependency to support
i.MX6SX which has NO PU regulator.
Enable devfreq cooling to trigger GPU freq change when
hot trip is reached.
Make sure thermal driver loaded after cpufreq is loaded,
otherwise, cpu_cooling will not get valid cpufreq table,
hence cpu_cooling will be not working.
Anson Huang [Wed, 18 Jun 2014 05:04:23 +0000 (13:04 +0800)]
ENGR00318913-3 thermal: imx: enable thermal support for i.mx6sx
i.MX6SX has some new feature of thermal interrupt function,
there is LOW, HIGH and PANIC irq for thermal sensor, so add
platform data to separate different thermal version;
The reset value of LOW ALARM is 0 which means the highest
temp, so the LOW ALARM will be triggered once irq is enabled,
so we need to set them to correct setting before enabling
thermal irq;
Enable PANIC ALARM as critical trip point, it will trigger
system reset via SRC module once PANIC IRQ is triggered.
Anson Huang [Wed, 18 Jun 2014 03:21:45 +0000 (11:21 +0800)]
ENGR00318913-2 thermal: imx: make thermal trip temp changeable
Make all thermal trips' temp changeable:
1. Different users may have different definitions about the
trip temp;
2. For testing purpose, if we want to test cooling device's
function, it is easy to change trip temp to cheat the cooling
device to active, otherwise, need to test it using heating box
which is very inconvenient
Anson Huang [Wed, 18 Jun 2014 03:09:47 +0000 (11:09 +0800)]
ENGR00318913-1 thermal: imx: update trip temp using default setting
Previously, the critical and passive trip temp settings are from
calibration data of hot point, but the lastest chips are only
calibrated at 25C and use an universal formula to get real temp,
so there is no longer a hot point value in calibration data, need
to set the critical and passive trip temp manually instead of
getting them from calibration data.
Currently the default setting for passive trip temp is 85 C, and
critical trip temp is 20 C higher than passive trip temp, which
is 105 C.
ENGR00318895-8 mtd: fsl-quadspi: add the DDR quad read support for Spansion NOR
Add the DDR quad read support for the fsl-quadspi driver.
Check the "spi-nor,ddr-quad-read-dummy" DT property, if the DT node is exit,
it means we could enable the DDR quad read.
(1) Test this patch with imx6sx-sdb board (Spansion s25fl128s)
The clock rate is 66MHz.
(2) The information of NOR flash:
-----------------------------------------------
root@imx6qdlsolo:~# mtdinfo /dev/mtd0
mtd0
Name: 21e4000.qspi
Type: nor
Eraseblock size: 65536 bytes, 64.0 KiB
Amount of eraseblocks: 256 (16777216 bytes, 16.0 MiB)
Minimum input/output unit size: 1 byte
Sub-page size: 1 byte
Character device major/minor: 90:0
Bad blocks are allowed: false
Device is writable: true
-----------------------------------------------
(3) Test this patch set with UBIFS & bonnie++:
-----------------------------------------------
ubiattach /dev/ubi_ctrl -m 0
ubimkvol /dev/ubi0 -N test -m
mount -t ubifs ubi0:test tmp
bonnie++ -d tmp -u 0 -s 10 -r 5
-----------------------------------------------
[3] add set_ddr_quad_mode() to initialize for the DDR quad read.
Currently it only works for Spansion NOR.
[3] about the dummy cycles.
We set the dummy with 8 for DDR quad read by default.
The m25p80.c can not support the DDR quad read, but the SPI NOR controller
can set the dummy value in its child DT node, and the SPI NOR framework
can parse it out.
ENGR00318895-3 mtd: spi-nor: add a new field for spi_nor{}
We need the SPI NOR child node to store some specific features, such as the
dummy cycles for the DDR Quad read.
But now, we only have the @dev field in the spi_nor{}. The @dev may points to a
spi_device{} for m25p80, while it may points to a platform_deivice{} for the
SPI NOR controller, such as fsl_quadspi.c.
It is not convenient for us to get come information from the SPI NOR flash.
This patch adds a new field @np to spi_nor{}, it points to the child node for
the SPI NOR flash.
ENGR00318895-1 mtd: spi-nor: read 6 bytes for the ID
Currently, we read 5 bytes for ID, but s25fl128s has the same ext_id(0x4d01)
with s25fl129p1. The s25fl128s can support the DDR Quad read, while s25fl129p1
does not. So we have to distinguish the two NOR flashs.
This patch reads out 6 bytes for the ID, and use the 6 bytes ID to search the
right flash_info.
The detail of the patch is:
[1] change the "ext_id" from u16 to u32.
We can store two bytes or three bytes with the @ext_id now.
[2] search the right flash_info with the 6byte ID and the new @ext_id.
We use "matched" variable to track the legacy two bytes @ext_id.
If the flash_info's @ext_id is three bytes, we will use the
sixth byte of the ID to check it.
[3] add the new item to spi_nor_ids for s25fl128s.
Timur Tabi [Fri, 13 Jun 2014 12:42:40 +0000 (07:42 -0500)]
ASoC: fsl-ssi: fix do_div build warning in fsl_ssi_set_bclk()
do_div() requires that the first parameter is a 64-bit integer,
which but clkrate was defined as an unsigned long. This caused
the following warnings:
CC sound/soc/fsl/fsl_ssi.o
sound/soc/fsl/fsl_ssi.c: In function 'fsl_ssi_set_bclk':
sound/soc/fsl/fsl_ssi.c:593:3: warning: comparison of distinct pointer types lacks a cast
sound/soc/fsl/fsl_ssi.c:593:3: warning: right shift count >= width of type
sound/soc/fsl/fsl_ssi.c:593:3: warning: passing argument 1 of '__div64_32' from incompatible pointer type
include/asm-generic/div64.h:35:17: note: expected 'uint64_t *' but argument is of type 'long unsigned int *'
Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit acf2c60a60b3d6d7080854b9483f37d99ded9b23) Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
projects / karo-tx-linux.git / log