Sekhar Nori [Tue, 22 Apr 2014 08:28:03 +0000 (13:58 +0530)]
ARM: l2c: AM43x: add L2 cache support
Add support for L2 cache controller (PL310) on AM437x SoC.
Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sekhar Nori [Tue, 22 Apr 2014 08:28:01 +0000 (13:58 +0530)]
ARM: l2c: omap2+: get rid of init call
Get rid of init call to initialize L2 cache. Instead use the init_early
machine hook. This helps in using the initialization routine across
SoCs without the need of ugly cpu_is_*() checks.
Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sekhar Nori [Tue, 22 Apr 2014 08:28:02 +0000 (13:58 +0530)]
ARM: l2c: omap2+: get rid of redundant cache replacement policy setting
L2 cache initialization for OMAP4 redundantly sets the cache policy to
Round-Robin. This is not needed since thats the PL310 default anyway.
Removing this reduces the number of platform specific aux control
settings.
Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Thu, 10 Apr 2014 23:48:25 +0000 (00:48 +0100)]
ARM: l2c: always enable non-secure access to lockdown registers
Since we always write to these during the cache initialisation, it is
a good idea to always have the non-secure access bit set. Set it in
core code and remove it from OMAP4. Remove the NS access bit for the
interrupt registers from OMAP4 as well - nothing in the kernel accesses
that yet, and we can add it in core code when we have the need.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 5 Apr 2014 09:57:44 +0000 (10:57 +0100)]
ARM: l2c: omap2: avoid reading directly from the L2 registers in platform code
Avoid reading directly from the L2 registers in platform code. The L2
code will have already saved the register values itself into the
l2x0_saved_regs structure, so platform code should just move these
values to where they're required.
This is safe because the L2x0 will have been initialised by an early
initcall, whereas the OMAP4 PM code is initialised late.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Fri, 28 Mar 2014 14:18:35 +0000 (14:18 +0000)]
ARM: l2c: move L2 cache register saving to a more sensible location
Move the L2 cache register saving to a more sensible location - after
the cache has been enabled, and fixups have been run. We move the
saving of the auxiliary control register into the ->save function as
well which makes everything operate in a sane and maintainable way.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Liu Hua [Fri, 18 Apr 2014 08:43:32 +0000 (09:43 +0100)]
ARM: 8031/2: change fixmap mapping region to support 32 CPUs
In 32-bit ARM systems, the fixmap mapping region can support no more
than 14 CPUs(total: 896k; one CPU: 64K). And we can configure NR_CPUS
up to 32. So there is a mismatch.
This patch moves fixmapping region downwards to region 0xffc00000-
0xffe00000. Then the fixmap mapping region can support up to 32 CPUs.
Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Liu Hua <sdu.liu@huawei.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Liu Hua [Fri, 18 Apr 2014 08:27:01 +0000 (09:27 +0100)]
ARM: 8031/1: fixmap: remove FIX_KMAP_BEGIN and FIX_KMAP_END
It seems that these two macros are not used by non architecture
specific code. And on ARM FIX_KMAP_BEGIN equals zero.
This patch removes these two macros. Instead, using FIX_KMAP_NR_PTES to
tell the pte number belonged to fixmap mapping region. The code will
become clearer when I introduce a bugfix on fixmap mapping region.
Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Liu Hua <sdu.liu@huawei.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Nicolas Pitre [Wed, 9 Apr 2014 20:24:02 +0000 (21:24 +0100)]
ARM: 8023/1: remove remnants of the static DMA mapping
It looks like the static mapping area for DMA was replaced by dynamic
allocation into the vmalloc area by commit e9da6e9905e6 but the
information in Documentation/arm/memory.txt was not removed accordingly.
CONSISTENT_END in arch/arm/include/asm/memory.h has no more users and
can be removed as well.
Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rabin Vincent [Thu, 3 Apr 2014 17:46:45 +0000 (18:46 +0100)]
ARM: 8022/1: ftrace: work with CONFIG_DEBUG_SET_MODULE_RONX
Make ftrace work with CONFIG_DEBUG_SET_MODULE_RONX by making module text
writable around the place where ftrace does its work, like it is done on
x86 in the patch which introduced CONFIG_DEBUG_SET_MODULE_RONX, 84e1c6bb38eb ("x86: Add RO/NX protection for loadable kernel modules").
Tested-by: Mitchel Humpherys <mitchelh@codeaurora.org> Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Enable hibernation for ARM architectures and provide ARM
architecture specific calls used during hibernation.
The swsusp hibernation framework depends on the
platform first having functional suspend/resume.
Then, in order to enable hibernation on a given platform, a
platform_hibernation_ops structure may need to be registered with
the system in order to save/restore any SoC-specific / cpu specific
state needing (re)init over a suspend-to-disk/resume-from-disk cycle.
For example:
- "secure" SoCs that have different sets of control registers
and/or different CR reg access patterns.
- SoCs with L2 caches as the activation sequence there is
SoC-dependent; a full off-on cycle for L2 is not done
by the hibernation support code.
- SoCs requiring steps on wakeup _before_ the "generic" parts
done by cpu_suspend / cpu_resume can work correctly.
- SoCs having persistent state which is maintained during suspend
and resume, but will be lost during the power off cycle after
suspend-to-disk.
This is a rebase/rework of Frank Hofmann's v5 hibernation patchset.
Acked-by: Russ Dill <Russ.Dill@ti.com> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Signed-off-by: Sebastian Capella <sebastian.capella@linaro.org> Acked-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[fixed duplicate virt_to_pfn() definition --rmk] Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Victor Kamensky [Tue, 22 Apr 2014 01:25:36 +0000 (02:25 +0100)]
ARM: 8033/1: fix big endian __pv_phys_pfn_offset size related issue
Fix e26a9e00afc482b971afcaef1db8c9034d4d6d7c 'ARM: Better
virt_to_page() handling' replaced __pv_phys_offset with
__pv_phys_pfn_offset. Also note that size of __pv_phys_offset
was quad but size of __pv_phys_pfn_offset is word. Instruction
that used to update __pv_phys_offset which address is in r6
had to update low word of __pv_phys_offset so it used #LOW_OFFSET
macro for store offset. Now when size of __pv_phys_pfn_offset is
word, no difference between little endian and big endian should
exist - i.e no offset should be used when __pv_phys_pfn_offset
is stored.
Note that for little endian image proposed change is noop,
since in little endian case #LOW_OFFSET is defined 0 anyway.
Reported-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Nicolas Pitre [Mon, 21 Apr 2014 23:25:35 +0000 (00:25 +0100)]
ARM: 8032/1: bL_switcher: fix validation check before its activation
The switcher should not depend on MAX_CLUSTER to determine ifit should
be activated or not. In a multiplatform kernel binary it is possible to
have dual-cluster and quad-cluster platforms configured in. In that case
MAX_CLUSTER which is a build time limit should be 4 and that shouldn't
prevent the switcher from working if the kernel is booted on a b.L
dual-cluster system.
In bL_switcher_halve_cpus() we already have a runtime validation check
to make sure we're dealing with only two clusters, so booting on a quad
cluster system will be caught and switcher activation aborted.
However, the b.L switcher must ensure the MCPM layer is initialized on
the booted hardware before doing anything. The mcpm_is_available()
function is added to that effect.
Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Abhilash Kesavan <kesavan.abhilash@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Liu Hua [Fri, 18 Apr 2014 06:45:36 +0000 (07:45 +0100)]
ARM: 8030/1: ARM : kdump : add arch_crash_save_vmcoreinfo
For vmcore generated by LPAE enabled kernel, user space
utility such as crash needs additional infomation to
parse.
So this patch add arch_crash_save_vmcoreinfo as what PAE enabled
i386 linux does.
Cc: <stable@vger.kernel.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Liu Hua <sdu.liu@huawei.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When viewed ftrace records, it will call the do_div(n, base) function, which achieved arch/arm/include/asm/div64.h in. When n = 10000000, base = 1000000, in do_div(n, base) will execute "umull %Q0, %R0, %1, %Q2".
Reviewed-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Cc: <stable@vger.kernel.org> # 2.6.20+ Signed-off-by: Alex Wu <wuquanming@huawei.com> Signed-off-by: Xiangyu Lu <luxiangyu@huawei.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Jay Foad [Mon, 14 Apr 2014 15:23:15 +0000 (16:23 +0100)]
ARM: 8026/1: Fix emulation of multiply accumulate instructions
The emulation for single and double precision multiply accumulate
instructions correctly normalised any denormal values in the operand
registers, but failed to normalise the destination (accumulator)
register.
This fixes https://bugzilla.kernel.org/show_bug.cgi?id=70501
Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
It is beneficial to have the L2 cache up and running earlier in the
system boot. Not only will this allow for simpler code when we come to
enable some features, but it also means that we get a more accurate
bogomips value for the udelay() loop. Calibrating the loop with the
L2 cache off, and then running with the L2 cache on is not the best
idea.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 14:07:12 +0000 (14:07 +0000)]
ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
As we have now removed all instances of the L2C-310 having its cache
size "modified" via platform/SoC code, discourage new cases showing
up by printing a warning.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 14:53:54 +0000 (14:53 +0000)]
ARM: l2c: realview: improve commentry about the L2 cache requirements
Add better commentry about the L2 cache requirements on these platforms.
Unfortunately, the auxiliary control register is not pre-set to indicate
the correct cache parameters, so we have to manually program these.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:44:41 +0000 (12:44 +0000)]
ARM: l2c: remove platforms/SoCs setting early BRESP
Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly. Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 15:39:09 +0000 (15:39 +0000)]
ARM: l2c: add automatic enable of early BRESP
The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted. Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.
Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 20:52:25 +0000 (20:52 +0000)]
ARM: l2c: fix register naming
We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices. Provide full auxiliary control register definitions.
Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 20:02:06 +0000 (20:02 +0000)]
ARM: l2c: implement L2C-310 erratum 752271 in core L2C code
Rather than having SoCs work around L2C erratum themselves, move them
into core code. This erratum affects the double linefill feature which
needs to be disabled for r3p0 to r3p1-50rel0.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that highbank uses the write_sec method, we don't need to enable
the L2 cache in SoC specific code; this can be done via the normal
mechanisms in the L2C code.
Checking with Rob Herring:
> > Can we kill the "highbank_smc1(0x102, 0x1);" here? That means
> > l2x0_of_init() will see the L2 cache disabled, and will try to enable
> > it via the write_sec hook, so it should do the right thing.
>
> Yes, that should work. You should be able to just call l2x0_of_init
> unconditionally. The condition was really to just avoid the smc on
> Midway which does get handled on h/w, but not if running virtualized.
So also drop the DT check too. I'm leaving the config check in place
so that if L2 is disabled, the write_sec hook can be optimised away.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that OMAP2 uses the write_sec method, we don't need to enable the L2
cache in OMAP2 specific code; this can be done via the normal mechanisms
in the L2C code. Remove the OMAP2 specific code.
Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 17:45:56 +0000 (17:45 +0000)]
ARM: l2c: omap2: implement new write_sec method
With the write_sec method, we no longer need to override the default
L2C disable method, and we no longer need the L2C set_debug method.
Both of these can be handled via the write_sec method.
Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 17:38:08 +0000 (17:38 +0000)]
ARM: l2c: provide generic hook to intercept writes to secure registers
When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort. Platforms normally have to call
firmware to work around this. Provide a hook for them to intercept
any L2C secure register write.
l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 23:04:10 +0000 (23:04 +0000)]
ARM: l2c: move type string into l2c_init_data structure
Rather than decoding this from the ID register, store it in the
l2c_init_data structure. This simplifies things some more, and
allows us to better provide further details as to how we're
driving the cache. We print the cache ID value anyway should we
need to precisely identify the cache hardware.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 22:44:38 +0000 (22:44 +0000)]
ARM: l2c: remove obsolete l2x0 ops for non-OF init
non-OF initialisation has never been used with any cache controller
which isn't an ARM cache controller, so we can safely get rid of the
old (and buggy) l2x0_*-based operations structure.
This is also the last reference to:
- l2x0_clean_line()
- l2x0_inv_line()
- l2x0_flush_line()
- l2x0_flush_all()
- l2x0_clean_all()
- l2x0_inv_all()
- l2x0_inv_range()
- l2x0_clean_range()
- l2x0_flush_range()
- l2x0_enable()
- l2x0_resume()
so kill those functions too.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 19:14:13 +0000 (19:14 +0000)]
ARM: l2c: convert Broadcom L2C-310 to new code
The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later. These
require no errata workarounds, and so we can directly call the l2c210
functions from their methods.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 21:29:28 +0000 (21:29 +0000)]
ARM: l2c: add L2C-220 specific handlers
The L2C-220 is different from the L2C-210 and L2C-310 in that every
operation is a background operation: this means we have to use
spinlocks to protect all operations, and we have to wait for every
operation to complete.
Should a second operation be attempted while a previous operation
is in progress, the response will be an imprecise abort.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 19:08:11 +0000 (19:08 +0000)]
ARM: l2c: implement L2C-310 erratum 588369 as a method override
Implement L2C-310 erratum 588369 by overriding the invalidate range
and flush range methods in the outer_cache operations structure.
This allows us to sensibly contain the erratum code in one place
without affecting other locations/implemetations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:18 +0000 (16:48 +0000)]
ARM: l2c: implement L2C-310 erratum 727915 as a method override
Implement L2C-310 erratum 727915 by overriding the flush_all method
in the outer_cache operations structure. This allows us to sensibly
contain the erratum code in one place without affecting other
locations or implementations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 18:55:53 +0000 (18:55 +0000)]
ARM: l2c: add L2C-210 specific handlers
Add L2C-210 specific cache operation handlers. These are tailored to
the requirements of the L2C-210 cache controller, which doesn't
require any workarounds. We avoid using the way operations during
normal operation, which means we can avoid locking: the only time
we use the way operations are during initialisation, and when
disabling the cache.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:13 +0000 (16:48 +0000)]
ARM: l2c: clean up save/resume functions
Rename the pl310 save/resume functions to have a l2c310 prefix - this
is it's official name. Use a local cached copy of the l2x0_base
virtual address, and also realise that many of the resume function
tails are the same as the enable functions, so make a call to the
enable function instead of duplicating that code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:11 +0000 (16:48 +0000)]
ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OF
Add the save/resume code hooks to the non-OF implementations as well.
There's no reason for the non-OF implementations to be any different
from the OF implementations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:07 +0000 (16:48 +0000)]
ARM: l2c: implement fixups for L2 cache controller quirks/errata
Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations can specify. This
helps to localise the quirks to those implementations which require
them.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:59 +0000 (16:47 +0000)]
ARM: l2c: move aurora broadcast setup to enable function
Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead. While here, clean
up that code and comments a little.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 17 Mar 2014 20:10:31 +0000 (20:10 +0000)]
ARM: l2c: only write the auxiliary control register if required
Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value. This allows us to
avoid invoking the platforms secure monitor code unnecessarily.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:57 +0000 (16:47 +0000)]
ARM: l2c: provide enable method
Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time. This allows us to remove a hack in
l2x0_unlock() for Marvell Aurora L2 caches.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:06 +0000 (16:48 +0000)]
ARM: l2c: group implementation specific code together
Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions in one
place, all the resume functions in another, all the OF parsing functions
some place else.
This makes it difficult to get an overview on what a particular
implementation is doing - grouping an implementations specific functions
together makes more sense, because you can see what it's doing without
the clutter of other implementations.
Organise it according to implementation.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:52 +0000 (16:47 +0000)]
ARM: l2c: clean up OF initialisation a bit
Rather than having a boolean and other tricks to disable some bits of
l2x0_init(), split this function into two parts: a common part shared
between OF and non-OF, and the non-OF part.
The common part can take a block of function pointers, and the cache
ID (to cope with Aurora's DT specified ID.) Eliminate the redundant
setting of l2x0_base in the OF case, moving it to the non-OF init
function.
This allows us to localise the OF-specific initialisation handling
from the non-OF handling.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:14 +0000 (16:48 +0000)]
ARM: l2c: rename cache_wait_way()
cache_wait_way() is actually used to wait for a particular mask to
report clear; it's not really got much to do with cache ways at all.
Indeed, it gets used to wait for the C bit to clear on older caches.
Rename this with a more generic function name which better reflects
its purpose: l2c_wait_mask().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:56 +0000 (16:47 +0000)]
ARM: l2c: provide generic helper for way-based operations
Provide a generic helper function for way based operations. These are
always background operations, and thus have to be waited for before a
new operation is commenced. This helper extracts that requirement from
several locations in the code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 17:19:21 +0000 (17:19 +0000)]
ARM: l2c: provide generic function for calling set_debug method
Provide a generic function which always calls the set_debug method.
This will be used later in the series as some work-arounds require
that the debug register be written.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 10:52:55 +0000 (10:52 +0000)]
ARM: outer cache: add documentation of outer cache functions
Add some documentation to cover the outer cache functions so that their
requirements can be better understood. Of particular note are the
flush_all() and disable() methods which must not be called except in
very specific circumstances.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 13:38:10 +0000 (13:38 +0000)]
ARM: l2c: omap2: remove ES1.0 support
Santosh says:
> But we should kill all of that since we long back decided to remove
> ES1.0 related code. The mach-omap code alreasy has removed the ES1.0
> compatibility so feel free to remove any specific ES1.0
> related stuff. That silicon is long dead.
Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Spear calls outer_flush_all() from it's SMP bringup function. This
is potentially dangerous as the L2C set/way operations which implement
this don't take kindly to concurrent operations. Besides, there's
better solutions to this, as implemented on other platforms.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:45 +0000 (16:47 +0000)]
ARM: l2c: remove unnecessary call to outer_flush_all()
outer_disable() is defined to safely turn the L2 cache off without data
loss: this means that outer_flush_all() should never be called unless
you need to implement some special L2 cache disabling, and even then
only from your replacement L2 cache disable function.
Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:44 +0000 (16:47 +0000)]
ARM: l2c: remove outer_inv_all() method
No one ever calls this function anywhere in the kernel, so let's
completely remove it from the outer cache API and turn it into an
internal-only thing.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
projects / karo-tx-linux.git / log