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(parent: bc5ead8) | patch
drm/i915: HSW: allow PCH clock gating for suspend
authorImre Deak <imre.deak@intel.com>
Wed, 17 Apr 2013 11:04:50 +0000 (14:04 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 10 May 2013 19:56:35 +0000 (21:56 +0200)
commit7d708ee40a6b9ca1112a322e554c887df105b025
treece5a29a139c6e6c1c0c2d3e156ba3f8f48800baftree | snapshot
parentbc5ead8c09b51e85d110132495a9bfa58dc39dabcommit | diff
drm/i915: HSW: allow PCH clock gating for suspend

For the device to enter D3 we should enable PCH clock gating.

v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.c diff | blob | history
drivers/gpu/drm/i915/i915_drv.h diff | blob | history
drivers/gpu/drm/i915/intel_display.c diff | blob | history
drivers/gpu/drm/i915/intel_drv.h diff | blob | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | history
Beck SC1x5 Kernel