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(parent: e506a0c) | patch
drm/i915: adjust framebuffer base address on gen4+
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 5 Jul 2012 10:17:30 +0000 (12:17 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 5 Jul 2012 11:36:01 +0000 (13:36 +0200)
commitc2c75131244507c93f812862fdbd4f3a37139401
tree068e1aae4099aafe1a31948e382bf882af43d378tree | snapshot
parente506a0c6381f180858d2e343c3ed5c0bde8e84bacommit | diff
drm/i915: adjust framebuffer base address on gen4+

The tileoffset register only supports a limited offset in x/y of 4096,
so for giant screen configuration with a shared fb we wrap around.

Fix this by computing a linear offset in tiles (pages) and only use
the tileoffset register to offset within the tile.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
drivers/gpu/drm/i915/intel_display.c diff | blob | history
Beck SC1x5 Kernel