From 03dce881292f43b269f1f8acca69df2c4568ee5c Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 7 Jan 2014 16:14:09 +0200 Subject: [PATCH] drm/i915: Enable watermarks for BDW MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We forgot to intialize the watermark vfuncs for BDW, and hence the watermarks were never updated. Signed-off-by: Ville Syrjälä Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 78503157daf2..835f86386b95 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5627,6 +5627,17 @@ void intel_init_pm(struct drm_device *dev) } dev_priv->display.init_clock_gating = haswell_init_clock_gating; } else if (INTEL_INFO(dev)->gen == 8) { + if (dev_priv->wm.pri_latency[0] && + dev_priv->wm.spr_latency[0] && + dev_priv->wm.cur_latency[0]) { + dev_priv->display.update_wm = ilk_update_wm; + dev_priv->display.update_sprite_wm = + ilk_update_sprite_wm; + } else { + DRM_DEBUG_KMS("Failed to read display plane latency. " + "Disable CxSR\n"); + dev_priv->display.update_wm = NULL; + } dev_priv->display.init_clock_gating = gen8_init_clock_gating; } else dev_priv->display.update_wm = NULL; -- 2.39.5