From 061e6b7e5d22abe2e65d0dd1b6c7d817d377562b Mon Sep 17 00:00:00 2001 From: Mike Miller Date: Wed, 5 Oct 2011 11:42:41 +1100 Subject: [PATCH] cciss: add half second delay to PCI PM reset code After using PCI Power Management to reset the Smart Array in kdump kernels we need some delay. Otherwise we may think the board failed to reset and bail out. This affects all users with a Smart Array P600. Signed-off-by: Mike Miller Cc: Jens Axboe Signed-off-by: Andrew Morton --- drivers/block/cciss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index 6da7edea700a..461d82f6cd10 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c @@ -4550,13 +4550,13 @@ static int cciss_controller_hard_reset(struct pci_dev *pdev, pmcsr &= ~PCI_PM_CTRL_STATE_MASK; pmcsr |= PCI_D3hot; pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); - msleep(500); /* enter the D0 power management state */ pmcsr &= ~PCI_PM_CTRL_STATE_MASK; pmcsr |= PCI_D0; pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); + msleep(500); } return 0; } -- 2.39.5