From 0822f933735c1eee6adfc236c72f763f42ac0f3d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 21 Sep 2015 18:54:03 +0200 Subject: [PATCH] clk: imx6: retain early UART clocks during kernel init Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- drivers/clk/imx/clk-imx6q.c | 8 ++++++++ drivers/clk/imx/clk-imx6sl.c | 8 ++++++++ drivers/clk/imx/clk-imx6sx.c | 8 ++++++++ 3 files changed, 24 insertions(+) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index b2c1c047dc94..e9ba018ac6a3 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -130,6 +130,12 @@ static inline int clk_on_imx6dl(void) return of_machine_is_compatible("fsl,imx6dl"); } +static struct clk ** const uart_clks[] __initconst = { + &clk[IMX6QDL_CLK_UART_IPG], + &clk[IMX6QDL_CLK_UART_SERIAL], + NULL +}; + static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; @@ -541,5 +547,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED(CONFIG_PCI_IMX6)) clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); + + imx_register_uart_clocks(uart_clks); } CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index a0d4cf26cfa9..3c3333faae8e 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c @@ -184,6 +184,12 @@ void imx6sl_set_wait_clk(bool enter) imx6sl_enable_pll_arm(false); } +static struct clk ** const uart_clks[] __initconst = { + &clks[IMX6SL_CLK_UART], + &clks[IMX6SL_CLK_UART_SERIAL], + NULL +}; + static void __init imx6sl_clocks_init(struct device_node *ccm_node) { struct device_node *np; @@ -439,5 +445,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]); + + imx_register_uart_clocks(uart_clks); } CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 5b95c2c2bf52..f0ad8bbc12f8 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -135,6 +135,12 @@ static u32 share_count_ssi1; static u32 share_count_ssi2; static u32 share_count_ssi3; +static struct clk ** const uart_clks[] __initconst = { + &clks[IMX6SX_CLK_UART_IPG], + &clks[IMX6SX_CLK_UART_SERIAL], + NULL +}; + static void __init imx6sx_clocks_init(struct device_node *ccm_node) { struct device_node *np; @@ -557,5 +563,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + + imx_register_uart_clocks(uart_clks); } CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init); -- 2.39.2