From 0d79f4f490352f6e1500cdd12a3b0e8b17265bde Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 18 Jul 2013 12:13:40 -0700 Subject: [PATCH] ARM: tegra: Make cache line size SoC specific Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Signed-off-by: Thierry Reding Tested-by: Stephen Warren Reviewed-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 2 -- include/configs/tegra114-common.h | 3 +++ include/configs/tegra20-common.h | 3 +++ include/configs/tegra30-common.h | 3 +++ 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index ccd68a19fd..0aac14e1c3 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -17,8 +17,6 @@ #define CONFIG_TEGRA /* which is a Tegra generic machine */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include /* get chip and board defs */ /* diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 44e98e5019..c3de9a999e 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -18,6 +18,9 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * NS16550 Configuration */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index d5e9ee4062..b009a316b1 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -9,6 +9,9 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 5ac8816504..99acbfd28b 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -9,6 +9,9 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ -- 2.39.5