From 0f4d3d1155d9a5e71e74658ac50b61141e370cf3 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 14 Apr 2014 12:21:49 +0100 Subject: [PATCH] MIPS: smp-cps: flush cache after patching mips_cps_core_entry The start of mips_cps_core_entry is patched in order to provide the code with the address of the CM register region at a point where it will be running non-coherent with the rest of the system. However the cache wasn't being flushed after that patching which could in principle lead to secondary cores using an invalid CM base address. The patching is moved to cps_prepare_cpus since local_flush_icache_range has not been initialised at the point cps_smp_setup is called. Signed-off-by: Paul Burton --- arch/mips/kernel/smp-cps.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index c7879fbe9f5b..c3661ca5f25c 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -44,7 +44,6 @@ static void __init cps_smp_setup(void) { unsigned int ncores, nvpes, core_vpes; int c, v; - u32 *entry_code; /* Detect & record VPE topology */ ncores = mips_cm_numcores(); @@ -82,10 +81,6 @@ static void __init cps_smp_setup(void) /* Initialise core 0 */ mips_cps_core_init(); - /* Patch the start of mips_cps_core_entry to provide the CM base */ - entry_code = (u32 *)&mips_cps_core_entry; - UASM_i_LA(&entry_code, 3, (long)mips_cm_base); - /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); } @@ -93,9 +88,16 @@ static void __init cps_smp_setup(void) static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned ncores, core_vpes, c; + u32 *entry_code; mips_mt_set_cpuoptions(); + /* Patch the start of mips_cps_core_entry to provide the CM base */ + entry_code = (u32 *)&mips_cps_core_entry; + UASM_i_LA(&entry_code, 3, (long)mips_cm_base); + dma_cache_wback_inv((unsigned long)&mips_cps_core_entry, + (void *)entry_code - (void *)&mips_cps_core_entry); + /* Allocate core boot configuration structs */ ncores = mips_cm_numcores(); mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), -- 2.39.5