From 0fc0708a8a2e6ff5e9ab633185903831fe478994 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 9 Jul 2014 12:51:05 +0100 Subject: [PATCH] MIPS: smp-cps: Fix entry code cache flush for systems with coherent I/O The dma_cache_wback_inv function performs exactly as is required here, unless the system has coherent I/O in which case it's a no-op. Call the underlying cache writeback functions directly, which is arguably clearer anyway given that the code doesn't actually have anything to do with DMA in a strict sense. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7282/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cps.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index f9b53b4eaccb..e6e16a1d4add 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -14,13 +14,14 @@ #include #include -#include +#include #include #include #include #include #include #include +#include #include #include #include @@ -132,8 +133,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) entry_code = (u32 *)&mips_cps_core_entry; UASM_i_LA(&entry_code, 3, (long)mips_cm_base); uasm_i_addiu(&entry_code, 16, 0, cca); - dma_cache_wback_inv((unsigned long)&mips_cps_core_entry, - (void *)entry_code - (void *)&mips_cps_core_entry); + blast_dcache_range((unsigned long)&mips_cps_core_entry, + (unsigned long)entry_code); + bc_wback_inv((unsigned long)&mips_cps_core_entry, + (void *)entry_code - (void *)&mips_cps_core_entry); + __sync(); /* Allocate core boot configuration structs */ mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), -- 2.39.5