From 12d217c795071bfee483158e1397c57e8dc3cb76 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 3 May 2013 12:15:38 -0300 Subject: [PATCH] drm/i915: clear FPGA_DBG_RM_NOCLAIM when capturing error state In the error state function we read the registers without checking if the power well is on, so after doing this we have to clear the FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting it and printing an error message. The first version of this patch was checking for the power well state and then avoiding reading registers that were off, but the reviewers requested to just read the registers any way and then later clear the FPGA_DBG_RM_NOCLAIM bit. Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 260545cc5049..544d766f6ef3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9842,6 +9842,13 @@ intel_display_capture_error_state(struct drm_device *dev) error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); } + /* In the code above we read the registers without checking if the power + * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to + * prevent the next I915_WRITE from detecting it and printing an error + * message. */ + if (HAS_POWER_WELL(dev)) + I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); + return error; } -- 2.39.5