From 16e11b994635788042f963ca1822b7cf9cd9cc94 Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Tue, 27 Oct 2015 14:47:03 +0200 Subject: [PATCH] drm/i915/bxt: Expose DC5 entry count MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit For bxt CSR firmware exposes a count of dc5 entries. Expose it through debugs Signed-off-by: Mika Kuoppala Reviewed-by: Imre Deak Tested-by: Daniel Stone # SKL Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_debugfs.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bf04f5bda324..8096e96c7d35 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2818,6 +2818,9 @@ static int i915_dmc_info(struct seq_file *m, void *unused) I915_READ(SKL_CSR_DC3_DC5_COUNT)); seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(SKL_CSR_DC5_DC6_COUNT)); + } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { + seq_printf(m, "DC3 -> DC5 count: %d\n", + I915_READ(BXT_CSR_DC3_DC5_COUNT)); } intel_runtime_pm_put(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bbfc9d9a5b49..083991271060 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5700,6 +5700,7 @@ enum skl_disp_power_wells { /* DMC/CSR */ #define SKL_CSR_DC3_DC5_COUNT 0x80030 #define SKL_CSR_DC5_DC6_COUNT 0x8002C +#define BXT_CSR_DC3_DC5_COUNT 0x80038 /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) -- 2.39.5