From 1aedf1f6675bc47f969db30aab9dfa1c748732f4 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 23 Jul 2013 22:49:03 +0800 Subject: [PATCH] ENGR00240987: ARM: imx6q: initialize clocks for IPU This is a fast-forward porting from 3.5.7 kernel. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 8e795dea02ec..c05b39523766 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -476,6 +476,26 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_prepare_enable(clk[usbphy2_gate]); } + /* ipu clock initialization */ + clk_set_parent(clk[ldb_di0_sel], clk[pll2_pfd0_352m]); + clk_set_parent(clk[ldb_di1_sel], clk[pll2_pfd0_352m]); + clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); + clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); + clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); + clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); + clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); + clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); + clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); + clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); + if (cpu_is_imx6dl()) { + clk_set_rate(clk[pll3_pfd1_540m], 540000000); + clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]); + clk_set_parent(clk[axi_sel], clk[pll3_pfd1_540m]); + } else if (cpu_is_imx6q()) { + clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]); + clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]); + } + /* * Let's initially set up CLKO with OSC24M, since this configuration * is widely used by imx6q board designs to clock audio codec. -- 2.39.5