From 22869087463b31c73daf32f5570b928403469656 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 16 Apr 2014 08:25:56 -0300 Subject: [PATCH] ARM: dts: imx27-phytec-phycore-som: Move PMIC IRQ GPIO into a separate pin group The hardware is better described if we place the PMIC IRQ GPIO into its own pingroup. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index d7ed63c51c6c..33c5dc2be89b 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -69,6 +69,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mc13783"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; reg = <0>; spi-cs-high; spi-max-frequency = <20000000>; @@ -204,7 +206,6 @@ MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ - MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ >; }; @@ -251,6 +252,12 @@ >; }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ + >; + }; + pinctrl_ssi1: ssi1grp { fsl,pins = < MX27_PAD_SSI1_FS__SSI1_FS 0x0 -- 2.39.5