From 22bd1f7ef40a1c0f2ba796ba7cd80013adcb835d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 26 Apr 2012 11:19:03 -0600 Subject: [PATCH] ARM: dt: tegra seaboard: fix I2C2 SCL rate This I2C bus is used for EDID/DDC reads and other "slow" I2C devices. This requires a 100KHz SCL (clock) rate. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra-seaboard.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index 0f30fc9f2005..11aea885c1bb 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -281,7 +281,7 @@ }; i2c@7000c400 { - clock-frequency = <400000>; + clock-frequency = <100000>; }; i2c@7000c500 { -- 2.39.5