From 25ca3076410b23b69649a970951d20a56718f3f8 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Sat, 1 Sep 2012 18:46:00 +0200 Subject: [PATCH] MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x The current dividers in the code are wrong and this leads to broken CPU frequency calculation on boards where the fractional part is used. For example, if the SoC is running from a 40MHz reference clock, refdiv=1, nint=14, outdiv=0 and nfrac=31 the real frequency is 579.375MHz but the current code calculates 569.687MHz instead. Because the system time is indirectly related to the CPU frequency the broken computation causes drift in the system time. The correct divider is 2^6 for the CPU PLL and 2^10 for the DDR PLL. Use the correct values to fix the issue. Signed-off-by: Gabor Juhos Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4305/ Signed-off-by: Ralf Baechle --- arch/mips/ath79/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index b91ad3efe29e..d2728573e9fc 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -189,7 +189,7 @@ static void __init ar934x_clocks_init(void) AR934X_PLL_CPU_CONFIG_NFRAC_MASK; cpu_pll = nint * ath79_ref_clk.rate / ref_div; - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6)); + cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); cpu_pll /= (1 << out_div); pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); @@ -203,7 +203,7 @@ static void __init ar934x_clocks_init(void) AR934X_PLL_DDR_CONFIG_NFRAC_MASK; ddr_pll = nint * ath79_ref_clk.rate / ref_div; - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10)); + ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); ddr_pll /= (1 << out_div); clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); -- 2.39.5