From 26b8c07f59ceff7b4ca40fb4bbc81abff01e8cf0 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 30 Nov 2013 12:42:03 +0100 Subject: [PATCH] MIPS: BCM63XX: setup the HSSPI clock rate Properly set up the HSSPI clock rate depending on the SoC's PLL rate. Signed-off-by: Jonas Gorski Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/6177/ --- arch/mips/bcm63xx/clk.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index 37a621a634ee..637565284732 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -390,3 +390,21 @@ void clk_put(struct clk *clk) } EXPORT_SYMBOL(clk_put); + +#define HSSPI_PLL_HZ_6328 133333333 +#define HSSPI_PLL_HZ_6362 400000000 + +static int __init bcm63xx_clk_init(void) +{ + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + clk_hsspi.rate = HSSPI_PLL_HZ_6328; + break; + case BCM6362_CPU_ID: + clk_hsspi.rate = HSSPI_PLL_HZ_6362; + break; + } + + return 0; +} +arch_initcall(bcm63xx_clk_init); -- 2.39.5