From 287e78bf2a4b41cebbef2368d69df6e38da9cbf9 Mon Sep 17 00:00:00 2001 From: Nancy Chen Date: Tue, 14 Aug 2012 09:49:05 -0500 Subject: [PATCH] ENGR00220297 [MX6SL]: Fix AHB clock not correct after kernel boot 1. Fix AHB_CLK is not right after system up. ahb_clk is 49.5MHz after system up. It should be 132MHz. 2. Remove the voltage changes for VDDSOC_CAP since there are vddarm voltage changed in CPUFREQ and vddsoc voltage and vddarm voltage should meet the constraint condition: VDDSOC > VDDARM - 50mV. Therefore VDDSOC voltage changes will be implemented in CPUFREQ. Signed-off-by: Nancy Chen --- arch/arm/mach-mx6/bus_freq.c | 54 ++++----------------------------- arch/arm/mach-mx6/clock_mx6sl.c | 4 +-- 2 files changed, 8 insertions(+), 50 deletions(-) diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c index 51e1d3b14e62..83310c436d54 100644 --- a/arch/arm/mach-mx6/bus_freq.c +++ b/arch/arm/mach-mx6/bus_freq.c @@ -99,14 +99,11 @@ static struct clk *pll2; static struct clk *pll3_sw_clk; static struct clk *pll2_200; static struct clk *mmdc_ch0_axi; -struct regulator *vddsoc_cap_regulator; static struct delayed_work low_bus_freq_handler; static void reduce_bus_freq_handler(struct work_struct *work) { - int ret = 0; - if (low_bus_freq_mode || !low_freq_bus_used()) return; @@ -138,17 +135,6 @@ static void reduce_bus_freq_handler(struct work_struct *work) clk_disable(pll3); } else { - /* Set VDDSOC_CAP to 1.1V */ - ret = regulator_set_voltage(vddsoc_cap_regulator, 1100000, - 1100000); - if (ret < 0) { - printk(KERN_DEBUG - "COULD NOT DECREASE VDDSOC_CAP VOLTAGE!!!!\n"); - return; - } - - udelay(150); - arm_mem_clked_in_wait = true; /* Set periph_clk to be sourced from OSC_CLK */ @@ -172,7 +158,6 @@ static void reduce_bus_freq_handler(struct work_struct *work) } high_bus_freq_mode = 0; - med_bus_freq_mode = 0; } /* Set the DDR, AHB to 24MHz. * This mode will be activated only when none of the modules that @@ -198,8 +183,6 @@ int set_low_bus_freq(void) */ int set_high_bus_freq(int high_bus_freq) { - int ret = 0; - if (busfreq_suspended) return 0; @@ -224,23 +207,6 @@ int set_high_bus_freq(int high_bus_freq) return 0; if (cpu_is_mx6sl()) { - /* Set the voltage of VDDSOC to 1.2V as in normal mode. */ - ret = regulator_set_voltage(vddsoc_cap_regulator, 1200000, - 1200000); - if (ret < 0) { - printk(KERN_DEBUG - "COULD NOT INCREASE VDDSOC_CAP VOLTAGE!!!!\n"); - return ret; - } - - /* Need to wait for the regulator to come back up */ - /* - * Delay time is based on the number of 24MHz clock cycles - * programmed in the ANA_MISC2_BASE_ADDR for each - * 25mV step. - */ - udelay(150); - /* Set periph_clk to be sourced from pll2_pfd2_400M */ /* First need to set the divider before changing the */ /* parent if parent clock is larger than previous one */ @@ -260,7 +226,6 @@ int set_high_bus_freq(int high_bus_freq) clk_round_rate(mmdc_ch0_axi, DDR_MED_CLK)); high_bus_freq_mode = 1; - med_bus_freq_mode = 0; } else { clk_enable(pll3); if (high_bus_freq) { @@ -511,13 +476,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(mmdc_ch0_axi); } - vddsoc_cap_regulator = regulator_get(NULL, "cpu_vddsoc"); - if (IS_ERR(vddsoc_cap_regulator)) { - printk(KERN_ERR "%s: failed to get vddsoc_cap regulator\n", - __func__); - return PTR_ERR(vddsoc_cap_regulator); - } - err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); if (err) { printk(KERN_ERR @@ -533,6 +491,11 @@ static int __devinit busfreq_probe(struct platform_device *pdev) /* To make pll2_400 use count right, as when system enter 24M, it will disable pll2_400 */ clk_enable(pll2_400); + } else if (cpu_is_mx6sl()) { + /* Set med_bus_freq_mode to 1 since med_bus_freq_mode + is not supported as yet for MX6SL */ + high_bus_freq_mode = 1; + med_bus_freq_mode = 1; } else { high_bus_freq_mode = 1; med_bus_freq_mode = 0; @@ -587,14 +550,9 @@ static int __init busfreq_init(void) if (cpu_is_mx6q()) set_high_bus_freq(1); - else + else if (cpu_is_mx6dl()) set_high_bus_freq(0); - /* Make sure system can enter low bus mode if it should be in - low bus mode */ - if (low_freq_bus_used() && !low_bus_freq_mode) - set_low_bus_freq(); - printk(KERN_INFO "Bus freq driver Enabled\n"); return 0; } diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index 3b2d9e527625..7496882feeb1 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -2908,7 +2908,7 @@ static struct clk lcdif_pix_clk = { .set_rate = _clk_lcdif_pix_set_rate, .round_rate = _clk_epdc_lcdif_pix_round_rate, .get_rate = _clk_lcdif_pix_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static struct clk epdc_pix_clk = { @@ -2923,7 +2923,7 @@ static struct clk epdc_pix_clk = { .set_rate = _clk_epdc_pix_set_rate, .round_rate = _clk_epdc_lcdif_pix_round_rate, .get_rate = _clk_epdc_pix_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_spdif_round_rate(struct clk *clk, unsigned long rate) -- 2.39.5