From 2981795cc0c02d12d0e231bfe22480564b937cd5 Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Tue, 11 Jun 2013 17:03:14 +0100 Subject: [PATCH] vme: tsi148: CR/CSR logic arround the wrong way The logic in the init routine for the TSI148 is inverted. It isn't switching on the CR/CSR space when it should be and is reporting it's on when its not. Correct the logic to do the right thing. Reported-by: De Roo, Steven Signed-off-by: Martyn Welch Signed-off-by: Greg Kroah-Hartman --- drivers/vme/bridges/vme_tsi148.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/vme/bridges/vme_tsi148.c b/drivers/vme/bridges/vme_tsi148.c index 94ce64d7a5f6..c04600e26a38 100644 --- a/drivers/vme/bridges/vme_tsi148.c +++ b/drivers/vme/bridges/vme_tsi148.c @@ -2300,12 +2300,13 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); - if (crat & TSI148_LCSR_CRAT_EN) { + if (crat & TSI148_LCSR_CRAT_EN) + dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); + else { dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); iowrite32be(crat | TSI148_LCSR_CRAT_EN, bridge->base + TSI148_LCSR_CRAT); - } else - dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); + } /* If we want flushed, error-checked writes, set up a window * over the CR/CSR registers. We read from here to safely flush -- 2.39.5