From 2e7b00261f1bb1b4949be087310574fbd658392b Mon Sep 17 00:00:00 2001 From: Ranjani Vaidyanathan Date: Fri, 12 Oct 2012 05:40:03 -0500 Subject: [PATCH] ENGR00229441 MX6SL-Reset MMDC read FIFO in low power IDLE MMDC can clock in bad data due to the glitches caused by changing the setting of various DDR IO pads in low power IDLE to save power. Solution is to reset the MMDC read FIFO before the DDR exits self-refresh. Signed-off-by: Ranjani Vaidyanathan --- arch/arm/mach-mx6/mx6sl_wfi.S | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/mach-mx6/mx6sl_wfi.S b/arch/arm/mach-mx6/mx6sl_wfi.S index dc4107dff7e8..e8936b6862c8 100644 --- a/arch/arm/mach-mx6/mx6sl_wfi.S +++ b/arch/arm/mach-mx6/mx6sl_wfi.S @@ -99,6 +99,31 @@ str r6, [r1, #0x320] /* DRAM_RESET */ str r7, [r1, #0x5c8] /* GPR_CTLDS */ + /* Need to reset the FIFO to avoid MMDC lockup + * caused because of floating/changing the + * configuration of many DDR IO pads. + */ + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =0x83c + ldr r6, [r1, r7] + orr r6, r6, #0x80000000 + str r6, [r1, r7] +fifo_reset1_wait: + ldr r6, [r1, r7] + and r6, r6, #0x80000000 + cmp r6, #0 + bne fifo_reset1_wait + + /* reset FIFO a second time */ + ldr r6, [r1, r7] + orr r6, r6, #0x80000000 + str r6, [r1, r7] +fifo_reset2_wait: + ldr r6, [r1, r7] + and r6, r6, #0x80000000 + cmp r6, #0 + bne fifo_reset2_wait + .endm .macro sl_ddr_io_set_lpm -- 2.39.5