From 30e4227df6909f02de370fa4ad5ebf2e174e444e Mon Sep 17 00:00:00 2001 From: Francisco Munoz Date: Tue, 12 Jun 2012 14:59:31 -0500 Subject: [PATCH] ENGR00213293 : Enable WEIM NOR support on the imx6 ARD revb quad/solo. Added IOMUX,GPIO and early param support for the parallel nor to work on the imx6 revB quad/solo. Since the parallel NOR can clash with I2C3, and SPI, an early param was added to enable WEIM NOR chips using boot args. The Weim NOR needs a HW rework for it to work. This rework is going to disable the SPI NOR. Modified files: arch/arm/mach-mx6/board-mx6q_sabreauto.c arch/arm/mach-mx6/board-mx6q_sabreauto.h arch/arm/mach-mx6/board-mx6solo_sabreauto.h Signed-off-by: Francisco Munoz --- arch/arm/mach-mx6/board-mx6q_sabreauto.c | 53 ++++++-- arch/arm/mach-mx6/board-mx6q_sabreauto.h | 130 +++++++++---------- arch/arm/mach-mx6/board-mx6solo_sabreauto.h | 132 ++++++++++---------- 3 files changed, 180 insertions(+), 135 deletions(-) diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c index 8b4125d28a0f..656508f9fab8 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c @@ -103,6 +103,7 @@ #define SABREAUTO_CSI0_RST IMX_GPIO_NR(4, 5) #define SABREAUTO_DISP0_RESET IMX_GPIO_NR(5, 0) #define SABREAUTO_I2C3_STEER IMX_GPIO_NR(5, 4) +#define SABREAUTO_WEIM_NOR_WDOG1 IMX_GPIO_NR(4, 29) #define SABREAUTO_ANDROID_VOLDOWN IMX_GPIO_NR(5, 14) #define SABREAUTO_PMIC_INT IMX_GPIO_NR(5, 16) #define SABREAUTO_ALS_INT IMX_GPIO_NR(5, 17) @@ -139,6 +140,7 @@ static int can0_enable; static int uart3_en; static int tuner_en; static int spinor_en; +static int weimnor_en; static int __init spinor_enable(char *p) { @@ -147,6 +149,13 @@ static int __init spinor_enable(char *p) } early_param("spi-nor", spinor_enable); +static int __init weimnor_enable(char *p) +{ + weimnor_en = 1; + return 0; +} +early_param("weim-nor", weimnor_enable); + static int __init uart3_enable(char *p) { uart3_en = 1; @@ -1302,6 +1311,8 @@ static void __init mx6_board_init(void) iomux_v3_cfg_t *mipi_sensor_pads = NULL; iomux_v3_cfg_t *i2c3_pads = NULL; iomux_v3_cfg_t *tuner_pads = NULL; + iomux_v3_cfg_t *spinor_pads = NULL; + iomux_v3_cfg_t *weimnor_pads = NULL; int common_pads_cnt; int can0_pads_cnt; @@ -1309,6 +1320,8 @@ static void __init mx6_board_init(void) int mipi_sensor_pads_cnt; int i2c3_pads_cnt; int tuner_pads_cnt; + int spinor_pads_cnt; + int weimnor_pads_cnt; if (cpu_is_mx6q()) { common_pads = mx6q_sabreauto_pads; @@ -1316,12 +1329,16 @@ static void __init mx6_board_init(void) can1_pads = mx6q_sabreauto_can1_pads; mipi_sensor_pads = mx6q_sabreauto_mipi_sensor_pads; tuner_pads = mx6q_tuner_pads; + spinor_pads = mx6q_spinor_pads; + weimnor_pads = mx6q_weimnor_pads; common_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_pads); can0_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_can0_pads); can1_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_can1_pads); mipi_sensor_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_mipi_sensor_pads); tuner_pads_cnt = ARRAY_SIZE(mx6q_tuner_pads); + spinor_pads_cnt = ARRAY_SIZE(mx6q_spinor_pads); + weimnor_pads_cnt = ARRAY_SIZE(mx6q_weimnor_pads); if (board_is_mx6_reva()) { i2c3_pads = mx6q_i2c3_pads_rev_a; i2c3_pads_cnt = ARRAY_SIZE(mx6q_i2c3_pads_rev_a); @@ -1335,12 +1352,17 @@ static void __init mx6_board_init(void) can1_pads = mx6dl_sabreauto_can1_pads; mipi_sensor_pads = mx6dl_sabreauto_mipi_sensor_pads; tuner_pads = mx6dl_tuner_pads; + spinor_pads = mx6dl_spinor_pads; + weimnor_pads = mx6dl_weimnor_pads; common_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_pads); can0_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_can0_pads); can1_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_can1_pads); mipi_sensor_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_mipi_sensor_pads); tuner_pads_cnt = ARRAY_SIZE(mx6dl_tuner_pads); + spinor_pads_cnt = ARRAY_SIZE(mx6dl_spinor_pads); + weimnor_pads_cnt = ARRAY_SIZE(mx6dl_weimnor_pads); + if (board_is_mx6_reva()) { i2c3_pads = mx6dl_i2c3_pads_rev_a; i2c3_pads_cnt = ARRAY_SIZE(mx6dl_i2c3_pads_rev_a); @@ -1352,11 +1374,19 @@ static void __init mx6_board_init(void) BUG_ON(!common_pads); mxc_iomux_v3_setup_multiple_pads(common_pads, common_pads_cnt); - if (!spinor_en) { + + /*If at least one NOR memory is selected we don't configure IC23 PADS*/ + if (spinor_en) { + BUG_ON(!spinor_pads); + mxc_iomux_v3_setup_multiple_pads(spinor_pads, spinor_pads_cnt); + } else if (weimnor_en) { + BUG_ON(!weimnor_pads); + mxc_iomux_v3_setup_multiple_pads(weimnor_pads, + weimnor_pads_cnt); + } else { BUG_ON(!i2c3_pads); mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt); } - if (can0_enable) { BUG_ON(!can0_pads); mxc_iomux_v3_setup_multiple_pads(can0_pads, @@ -1376,12 +1406,19 @@ static void __init mx6_board_init(void) gpio_direction_output(SABREAUTO_I2C_EXP_RST, 1); if (!board_is_mx6_reva()) { - /* enable i2c3_sda route path */ + /* enable either EIM_D18 or i2c3_sda route path */ gpio_request(SABREAUTO_I2C3_STEER, "i2c3-steer"); if (spinor_en) gpio_direction_output(SABREAUTO_I2C3_STEER, 0); - else - gpio_direction_output(SABREAUTO_I2C3_STEER, 1); + else if (weimnor_en) { + /*Put DISP0_DAT8 in ALT5 mode to prevent WDOG1 of + resetting WEIM NOR*/ + gpio_direction_output(SABREAUTO_I2C3_STEER, 0); + + gpio_request(SABREAUTO_WEIM_NOR_WDOG1, "nor-reset"); + gpio_direction_output(SABREAUTO_WEIM_NOR_WDOG1, 1); + } else + gpio_direction_output(SABREAUTO_I2C3_STEER, 1); /* Set GPIO_16 input for IEEE-1588 ts_clk and * RMII reference clk * For MX6 GPR1 bit21 meaning: @@ -1449,10 +1486,10 @@ static void __init mx6_board_init(void) /* SPI */ imx6q_add_ecspi(0, &mx6q_sabreauto_spi_data); #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) - spi_device_init(); + spi_device_init(); #else - mx6q_setup_weimcs(); - platform_device_register(&physmap_flash_device); + mx6q_setup_weimcs(); + platform_device_register(&physmap_flash_device); #endif imx6q_add_mxc_hdmi(&hdmi_data); diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.h b/arch/arm/mach-mx6/board-mx6q_sabreauto.h index 4c74a6aba961..f3763a0bf38b 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.h +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.h @@ -215,69 +215,6 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = { MX6Q_PAD_ENET_TXD1__MLB_MLBCLK, MX6Q_PAD_GPIO_6__MLB_MLBSIG, MX6Q_PAD_GPIO_2__MLB_MLBDAT, - -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) - /* eCSPI1 */ - MX6Q_PAD_EIM_D16__ECSPI1_SCLK, - MX6Q_PAD_EIM_D17__ECSPI1_MISO, - MX6Q_PAD_EIM_D18__ECSPI1_MOSI, - MX6Q_PAD_EIM_D19__ECSPI1_SS1, - MX6Q_PAD_EIM_D19__GPIO_3_19, /*SS1*/ -#else - /* Parallel NOR */ - MX6Q_PAD_EIM_OE__WEIM_WEIM_OE, - MX6Q_PAD_EIM_RW__WEIM_WEIM_RW, - MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT, - MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0, - - MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA, - MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK, - /* Parallel Nor Data Bus */ - MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16, - MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17, - MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18, - MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19, - MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20, - MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21, - MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22, - MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23, - MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24, - MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25, - MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26, - MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27, - MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28, - MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29, - MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30, - MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31, - - /* Parallel Nor 25 bit Address Bus */ - MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24, - MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23, - MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22, - MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21, - MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20, - MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19, - MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18, - MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17, - MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16, - - MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15, - MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14, - MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13, - MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12, - MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11, - MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10, - MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9, - MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8, - MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7, - MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6, - MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5, - MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, - MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, - MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, - MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, - MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, -#endif }; static iomux_v3_cfg_t mx6q_sabreauto_can0_pads[] = { @@ -355,3 +292,70 @@ static iomux_v3_cfg_t mx6q_tuner_pads[] __initdata = { }; +static iomux_v3_cfg_t mx6q_spinor_pads[] __initdata = { + /* eCSPI1 */ + MX6Q_PAD_EIM_D16__ECSPI1_SCLK, + MX6Q_PAD_EIM_D17__ECSPI1_MISO, + MX6Q_PAD_EIM_D18__ECSPI1_MOSI, + MX6Q_PAD_EIM_D19__ECSPI1_SS1, + + MX6Q_PAD_EIM_D19__GPIO_3_19, +}; + +static iomux_v3_cfg_t mx6q_weimnor_pads[] __initdata = { + /* Parallel NOR */ + MX6Q_PAD_EIM_OE__WEIM_WEIM_OE, + MX6Q_PAD_EIM_RW__WEIM_WEIM_RW, + MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT, + MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0, + /*Control NOR reset using gpio mode*/ + MX6Q_PAD_DISP0_DAT8__GPIO_4_29, + + MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA, + MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK, + /* Parallel Nor Data Bus */ + MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16, + MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17, + MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18, + MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19, + MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20, + MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21, + MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22, + MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23, + MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24, + MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25, + MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26, + MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27, + MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28, + MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29, + MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30, + MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31, + + /* Parallel Nor 25 bit Address Bus */ + MX6Q_PAD_EIM_A24__GPIO_5_4, + MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23, + MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22, + MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21, + MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20, + MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19, + MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18, + MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17, + MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16, + + MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15, + MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14, + MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13, + MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12, + MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11, + MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10, + MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9, + MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8, + MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7, + MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6, + MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5, + MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, + MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, + MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, + MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, + MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, +}; diff --git a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h index dd113bab749b..3b2e247b3735 100644 --- a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h +++ b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h @@ -215,70 +215,6 @@ static iomux_v3_cfg_t mx6dl_sabreauto_pads[] = { MX6DL_PAD_ENET_TXD1__MLB_MLBCLK, MX6DL_PAD_GPIO_6__MLB_MLBSIG, MX6DL_PAD_GPIO_2__MLB_MLBDAT, - -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) - /* eCSPI1 */ - MX6DL_PAD_EIM_D16__ECSPI1_SCLK, - MX6DL_PAD_EIM_D17__ECSPI1_MISO, - MX6DL_PAD_EIM_D18__ECSPI1_MOSI, - MX6DL_PAD_EIM_D19__ECSPI1_SS1, - - MX6DL_PAD_EIM_D19__GPIO_3_19, -#else - /* Parallel NOR */ - MX6DL_PAD_EIM_OE__WEIM_WEIM_OE, - MX6DL_PAD_EIM_RW__WEIM_WEIM_RW, - MX6DL_PAD_EIM_WAIT__WEIM_WEIM_WAIT, - MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0, - - MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA, - MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK, - /* Parallel Nor Data Bus */ - MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16, - MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17, - MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18, - MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19, - MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20, - MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21, - MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22, - MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23, - MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24, - MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25, - MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26, - MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27, - MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28, - MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29, - MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30, - MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31, - - /* Parallel Nor 25 bit Address Bus */ - MX6DL_PAD_EIM_A24__WEIM_WEIM_A_24, - MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23, - MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22, - MX6DL_PAD_EIM_A21__WEIM_WEIM_A_21, - MX6DL_PAD_EIM_A20__WEIM_WEIM_A_20, - MX6DL_PAD_EIM_A19__WEIM_WEIM_A_19, - MX6DL_PAD_EIM_A18__WEIM_WEIM_A_18, - MX6DL_PAD_EIM_A17__WEIM_WEIM_A_17, - MX6DL_PAD_EIM_A16__WEIM_WEIM_A_16, - - MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15, - MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14, - MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13, - MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12, - MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11, - MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10, - MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9, - MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8, - MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7, - MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6, - MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5, - MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, - MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, - MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, - MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, - MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, -#endif }; static iomux_v3_cfg_t mx6dl_sabreauto_can0_pads[] = { @@ -355,3 +291,71 @@ static iomux_v3_cfg_t mx6dl_tuner_pads[] __initdata = { MX6DL_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS, MX6DL_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD, }; + +static iomux_v3_cfg_t mx6dl_spinor_pads[] __initdata = { + /* eCSPI1 */ + MX6DL_PAD_EIM_D16__ECSPI1_SCLK, + MX6DL_PAD_EIM_D17__ECSPI1_MISO, + MX6DL_PAD_EIM_D18__ECSPI1_MOSI, + MX6DL_PAD_EIM_D19__ECSPI1_SS1, + + MX6DL_PAD_EIM_D19__GPIO_3_19, +}; + +static iomux_v3_cfg_t mx6dl_weimnor_pads[] __initdata = { + /* Parallel NOR */ + MX6DL_PAD_EIM_OE__WEIM_WEIM_OE, + MX6DL_PAD_EIM_RW__WEIM_WEIM_RW, + MX6DL_PAD_EIM_WAIT__WEIM_WEIM_WAIT, + MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0, + /*Control NOR reset using gpio mode*/ + MX6DL_PAD_DISP0_DAT8__GPIO_4_29, + + MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA, + MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK, + /* Parallel Nor Data Bus */ + MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16, + MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17, + MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18, + MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19, + MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20, + MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21, + MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22, + MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23, + MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24, + MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25, + MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26, + MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27, + MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28, + MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29, + MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30, + MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31, + + /* Parallel Nor 25 bit Address Bus */ + MX6DL_PAD_EIM_A24__GPIO_5_4, + MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23, + MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22, + MX6DL_PAD_EIM_A21__WEIM_WEIM_A_21, + MX6DL_PAD_EIM_A20__WEIM_WEIM_A_20, + MX6DL_PAD_EIM_A19__WEIM_WEIM_A_19, + MX6DL_PAD_EIM_A18__WEIM_WEIM_A_18, + MX6DL_PAD_EIM_A17__WEIM_WEIM_A_17, + MX6DL_PAD_EIM_A16__WEIM_WEIM_A_16, + + MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15, + MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14, + MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13, + MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12, + MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11, + MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10, + MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9, + MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8, + MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7, + MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6, + MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5, + MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, + MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, + MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, + MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, + MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, +}; -- 2.39.5