From 36af995496b441a0f50010c5151ebe2f2b178fb1 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Thu, 13 Sep 2012 17:23:04 +0200 Subject: [PATCH] EDAC: Handle csrow/channel on csbased MCIs differently The csrow and channel on csbased memory controllers get reported in the top_layer and mid_layer arguments. If we rely on the dimm->csrow, we get wrong csrows incremented in sysfs. For example, for an injection to csrow 1 on MCT 1: [ 5448.720258] EDAC MC1: 1 CE on mc#1csrow#1channel#1 (csrow:1 channel:1 page:0x827c43 offset:0xca0 grain:0 syndrome:0x1c6) we get [ 5448.720244] EDAC DEBUG: edac_mc_handle_error: rank csrows map: (3,0) [ 5448.720248] EDAC DEBUG: edac_mc_handle_error: csrow/channel to increment: (3,0) csrow 3, channel 0 to increment mc1/csrow3/ce_count sysfs counter. Fix this by reading the csrow number directly. Signed-off-by: Borislav Petkov --- drivers/edac/edac_mc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 39c75246c2ae..7b8ea79c78a7 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1182,6 +1182,12 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, if (!enable_per_layer_report) { strcpy(label, "any memory"); } else { + + if (mci->csbased) { + row = top_layer; + chan = mid_layer; + } + edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); if (p == label) strcpy(label, "unknown memory"); -- 2.39.5