From 38d811545c61cf188beac860615a08fb32f73eb1 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Fri, 23 May 2014 13:16:45 -0700 Subject: [PATCH] drm/i915/vlv: add pll assertion when disabling DPIO common well MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit When doing this, all PLLs should be disabled. Signed-off-by: Jesse Barnes Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7f5e86ff2b64..1fad1750a46a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5904,9 +5904,11 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, void __vlv_set_power_well(struct drm_i915_private *dev_priv, enum punit_power_well power_well_id, bool enable) { + struct drm_device *dev = dev_priv->dev; u32 mask; u32 state; u32 ctrl; + enum pipe pipe; if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) { if (enable) { @@ -5920,6 +5922,8 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv, DPLL_INTEGRATED_CRI_CLK_VLV); udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ } else { + for_each_pipe(pipe) + assert_pll_disabled(dev_priv, pipe); /* Assert common reset */ I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); -- 2.39.5