From 3cbdb48fbe7f975d96cfd7dddc3bfb17c9a01583 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Mon, 19 Jan 2015 13:50:49 +0200 Subject: [PATCH] drm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable the RP down timeout interrupt, and says that the timeout value is hence not used. We do enable that interrupt currently though, so leaving the timeout as 0 results in very poor performance as the GPU frequency keeps dropping constantly. So just program the register with the recommended value. Leaving the interrupt enabled doesn't seem to do any harm so far. So I've decided to leave it on for now, just to avoid making CHV a special case. This fixes the performance regression from: commit 5a0afd4b78ec23f27f5d486ac3d102c2e8d66bd7 Author: Deepak S Date: Sat Dec 13 11:43:27 2014 +0530 drm/i915/chv: Use timeout mode for RC6 on chv Cc: Deepak S Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ee9a5f95e5d2..8c7a07d3930f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4743,6 +4743,7 @@ static void cherryview_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_CONTROL, rc6_mode); /* 4 Program defaults and thresholds for RPS*/ + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); I915_WRITE(GEN6_RP_UP_EI, 66000); -- 2.39.5