From 3e1f72664e0a8a31e9b90c48459deb6642fd52f3 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 3 May 2013 17:23:44 -0300 Subject: [PATCH] drm/i915: MCH_SSKPD is a 64 bit register on Haswell MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit And the SNB_READ_WM0_LATENCY macro is not valid anymore because we have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if the new one is not zero. Signed-off-by: Paulo Zanoni Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ad1d35526a8f..912ab4d8d722 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4633,7 +4633,7 @@ void intel_init_pm(struct drm_device *dev) } dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; } else if (IS_HASWELL(dev)) { - if (SNB_READ_WM0_LATENCY()) { + if (I915_READ64(MCH_SSKPD)) { dev_priv->display.update_wm = haswell_update_wm; dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; } else { -- 2.39.5