From 4a9d0b033702566cde2f33ed19ff9c8a90b7fe8f Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 15 Jan 2016 21:49:53 +0800 Subject: [PATCH] ARM: dts: rockchip: add the sdio power sequence for kylin board This patch adds the sdio power sequence for kylin board. The WLAN attached to a SDIO interface, wifi/bluetooth have reset and power been needed to enable. AFAIK, the simple power sequence provider sets a value for multiple GPIOs. So the reset and power of WlAN chip can be handled in mmc power sequence. On the module itself this is one of these, that should can be handled by reset GPIOs in simple mmc power sequence. The Bluetooth host wake is high active from bootup, this patch is also set pinctrl bias as the default to enable the pull up in soc internal. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 905e187da381..6a32b234525a 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -46,6 +46,23 @@ model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_wake_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - SDIO_RESET_L_WL_RST + * - SDIO_RESET_L_BT_EN + */ + reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ + <&gpio0 27 GPIO_ACTIVE_LOW>, /* WL_RST */ + <&gpio2 9 GPIO_ACTIVE_LOW>; /* BT_EN */ + }; + sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -303,6 +320,7 @@ cap-sdio-irq; default-sample-phase = <90>; keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; non-removable; num-slots = <1>; pinctrl-names = "default"; @@ -336,6 +354,12 @@ }; }; + sdio { + bt_wake_h: bt-wake-h { + rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + sleep { global_pwroff: global-pwroff { rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>; -- 2.39.5