From 4e96fcd209b64b43c80c83743f124d9370d77bf2 Mon Sep 17 00:00:00 2001 From: Kouei Abe Date: Fri, 31 Aug 2012 15:13:19 +0900 Subject: [PATCH] arm: Add ARM ERRATA 775420 workaround Signed-off-by: Kouei Abe Signed-off-by: Simon Horman --- arch/arm/Kconfig | 10 ++++++++++ arch/arm/kernel/entry-armv.S | 17 +++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2f88d8d97701..74fbdf73abb8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419 on systems with an outer cache, the store buffer is drained explicitly. +config ARM_ERRATA_775420 + bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 775420 Cortex-A9 (r2p2, + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance + operation aborts with MMU exception, it might cause the processor + deadlock. This workaround puts DSB before executing ISB at the + beginning of the abort exception handler. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 0f82098c9bfe..070fa625c5f2 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -989,10 +989,19 @@ __kuser_helper_end: * SP points to a minimal amount of processor-private memory, the address * of which is copied into r0 for the mode specific abort handler. */ +#ifdef CONFIG_ARM_ERRATA_775420 + .macro vector_stub, name, mode, correction=0, abort=0 +#else .macro vector_stub, name, mode, correction=0 +#endif .align 5 vector_\name: +#ifdef CONFIG_ARM_ERRATA_775420 + .if \abort + dsb + .endif +#endif .if \correction sub lr, lr, #\correction .endif @@ -1056,7 +1065,11 @@ __stubs_start: * Data abort dispatcher * Enter in ABT mode, spsr = USR CPSR, lr = USR PC */ +#ifdef CONFIG_ARM_ERRATA_775420 + vector_stub dabt, ABT_MODE, 8, 1 +#else vector_stub dabt, ABT_MODE, 8 +#endif .long __dabt_usr @ 0 (USR_26 / USR_32) .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) @@ -1079,7 +1092,11 @@ __stubs_start: * Prefetch abort dispatcher * Enter in ABT mode, spsr = USR CPSR, lr = USR PC */ +#ifdef CONFIG_ARM_ERRATA_775420 + vector_stub pabt, ABT_MODE, 4, 1 +#else vector_stub pabt, ABT_MODE, 4 +#endif .long __pabt_usr @ 0 (USR_26 / USR_32) .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) -- 2.39.5