From 53d9ebe1f3038b975309671aabca467d5376ba5a Mon Sep 17 00:00:00 2001 From: Ryan QIAN Date: Wed, 16 May 2012 15:01:47 +0800 Subject: [PATCH] ENGR00209483 [imx6sl]: add USDHC support - add SD1, SD2 and SD3 support to mx6sl. Signed-off-by: Ryan QIAN --- arch/arm/mach-mx6/board-mx6sl_arm2.c | 31 +++++++++++++++++++++++++ arch/arm/mach-mx6/board-mx6sl_arm2.h | 34 ++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c index 2fa33af41969..2298e17315d8 100755 --- a/arch/arm/mach-mx6/board-mx6sl_arm2.c +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c @@ -73,11 +73,42 @@ #include "cpu_op-mx6.h" #include "board-mx6sl_arm2.h" +#define MX6_ARM2_SD1_WP IMX_GPIO_NR(4, 6) /* KEY_COL7 */ +#define MX6_ARM2_SD1_CD IMX_GPIO_NR(4, 7) /* KEY_ROW7 */ +#define MX6_ARM2_SD2_WP IMX_GPIO_NR(4, 29) /* SD2_DAT6 */ +#define MX6_ARM2_SD2_CD IMX_GPIO_NR(5, 0) /* SD2_DAT7 */ +#define MX6_ARM2_SD3_CD IMX_GPIO_NR(3, 22) /* REF_CLK_32K */ + +static const struct esdhc_platform_data mx6_arm2_sd1_data __initconst = { + .cd_gpio = MX6_ARM2_SD1_CD, + .wp_gpio = MX6_ARM2_SD1_WP, + .support_8bit = 1, + .keep_power_at_suspend = 1, + .delay_line = 0, +}; + +static const struct esdhc_platform_data mx6_arm2_sd2_data __initconst = { + .cd_gpio = MX6_ARM2_SD2_CD, + .wp_gpio = MX6_ARM2_SD2_WP, + .keep_power_at_suspend = 1, + .delay_line = 0, +}; + +static const struct esdhc_platform_data mx6_arm2_sd3_data __initconst = { + .cd_gpio = MX6_ARM2_SD3_CD, + .keep_power_at_suspend = 1, + .delay_line = 0, +}; + void __init early_console_setup(unsigned long base, struct clk *clk); static inline void mx6_arm2_init_uart(void) { imx6q_add_imx_uart(0, NULL); /* DEBUG UART1 */ + + imx6q_add_sdhci_usdhc_imx(0, &mx6_arm2_sd1_data); + imx6q_add_sdhci_usdhc_imx(1, &mx6_arm2_sd2_data); + imx6q_add_sdhci_usdhc_imx(2, &mx6_arm2_sd3_data); } /*! diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.h b/arch/arm/mach-mx6/board-mx6sl_arm2.h index 84268850336c..c2e6a28aa367 100755 --- a/arch/arm/mach-mx6/board-mx6sl_arm2.h +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.h @@ -24,6 +24,40 @@ static iomux_v3_cfg_t mx6sl_arm2_pads[] = { /* UART1 */ MX6SL_PAD_UART1_RXD__UART1_RXD, MX6SL_PAD_UART1_TXD__UART1_TXD, + + /* SD1 */ + MX6SL_PAD_SD1_CLK__USDHC1_CLK, + MX6SL_PAD_SD1_CMD__USDHC1_CMD, + MX6SL_PAD_SD1_DAT0__USDHC1_DAT0, + MX6SL_PAD_SD1_DAT1__USDHC1_DAT1, + MX6SL_PAD_SD1_DAT2__USDHC1_DAT2, + MX6SL_PAD_SD1_DAT3__USDHC1_DAT3, + MX6SL_PAD_SD1_DAT4__USDHC1_DAT4, + MX6SL_PAD_SD1_DAT5__USDHC1_DAT5, + MX6SL_PAD_SD1_DAT6__USDHC1_DAT6, + MX6SL_PAD_SD1_DAT7__USDHC1_DAT7, + /* SD1 CD & WP */ + MX6SL_PAD_KEY_ROW7__GPIO_4_7, + MX6SL_PAD_KEY_COL7__GPIO_4_6, + /* SD2 */ + MX6SL_PAD_SD2_CLK__USDHC2_CLK, + MX6SL_PAD_SD2_CMD__USDHC2_CMD, + MX6SL_PAD_SD2_DAT0__USDHC2_DAT0, + MX6SL_PAD_SD2_DAT1__USDHC2_DAT1, + MX6SL_PAD_SD2_DAT2__USDHC2_DAT2, + MX6SL_PAD_SD2_DAT3__USDHC2_DAT3, + /* SD2 CD & WP */ + MX6SL_PAD_SD2_DAT7__GPIO_5_0, + MX6SL_PAD_SD2_DAT6__GPIO_4_29, + /* SD3 */ + MX6SL_PAD_SD3_CLK__USDHC3_CLK, + MX6SL_PAD_SD3_CMD__USDHC3_CMD, + MX6SL_PAD_SD3_DAT0__USDHC3_DAT0, + MX6SL_PAD_SD3_DAT1__USDHC3_DAT1, + MX6SL_PAD_SD3_DAT2__USDHC3_DAT2, + MX6SL_PAD_SD3_DAT3__USDHC3_DAT3, + /* SD3 CD */ + MX6SL_PAD_REF_CLK_32K__GPIO_3_22, }; #endif -- 2.39.5