From 567ac52f15e8f2a1379a689b3f82b7ce11c19beb Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Tue, 9 Sep 2014 14:36:12 +0800 Subject: [PATCH] ENGR00329844-02 ARM: dts: imx6q: add uart5 dte set for sabresd board Add uart5 DTE mode pinctrl set for imx6q-sabresd board. Since there have pin confliction, so add new dts file. (cherry picked from commit d63b40d5b1b05992d2328ef0bdc80ec5d96f2dce) Signed-off-by: Fugang Duan --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-sabresd-uart.dts | 23 +++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 18 ++++++++++++++++++ 3 files changed, 42 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-sabresd-uart.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a4eb75dfac73..0b28c353a66a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ imx6q-sabresd-enetirq.dtb \ + imx6q-sabresd-uart.dtb \ imx6q-sabresd-hdcp.dtb \ imx6q-sabresd-ldo.dtb \ imx6q-sbc6x.dtb \ diff --git a/arch/arm/boot/dts/imx6q-sabresd-uart.dts b/arch/arm/boot/dts/imx6q-sabresd-uart.dts new file mode 100644 index 000000000000..800479da5941 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabresd-uart.dts @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabresd.dts" + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&ecspi1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index c2e97246ff96..a1816d75af7f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -409,6 +409,24 @@ >; }; + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 -- 2.39.5