From 568adaa56f2a41a7d1b1b26ab9b453e2cd487a8c Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Fri, 15 Nov 2013 14:31:11 +0800 Subject: [PATCH] ARM: dts: imx: specify the value of audmux pinctrl instead of 0x80000000 We must specify the value of audmux pinctrl if we want to use pinctrl_pm(). Thus change bypass value 0x80000000 to what we exactly need. This patch also seperately unset PUE bit for TXD so that IOMUX won't pull up/down the pin after turning into tristate. When we use SSI normal mode to playback monaural audio via I2S signal, there'd be a pulled curve occur to its signal at the second slot if setting PUE bit for TXD. And it will make the second channel to play a constant noise. So by keeping the signal level in the second slot, we can get a constant high level signal (-1) or a low level one (0). Signed-off-by: Nicolin Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-pingrp.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-pingrp.h b/arch/arm/boot/dts/imx6qdl-pingrp.h index a326e93a2a14..d111e598cad1 100644 --- a/arch/arm/boot/dts/imx6qdl-pingrp.h +++ b/arch/arm/boot/dts/imx6qdl-pingrp.h @@ -11,26 +11,26 @@ #define __DTS_IMX6QDL_PINGRP_H #define MX6QDL_AUDMUX_PINGRP1 \ - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 \ - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 \ - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 \ - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 \ + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 \ + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 \ + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 #define MX6QDL_AUDMUX_PINGRP2 \ - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 \ - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 \ - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 \ - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 \ + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 \ + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 \ + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 #define MX6QDL_AUDMUX_PINGRP3 \ - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 \ - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 \ - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 \ + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 \ + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 \ + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 \ #define MX6QDL_AUDMUX_PINGRP4 \ - MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x80000000 \ - MX6QDL_PAD_EIM_D25__AUD5_RXC 0x80000000 \ - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 + MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 \ + MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 \ + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 #define MX6QDL_ECSPI1_PINGRP1 \ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 \ -- 2.39.5